Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005RSVVRWXYabddqppdpipsqssdGeneral purpose register specified by the ModRM r/mfield. The ModRM mod field must be 11b.Segment register specified by the ModRM reg field.128-bit XMM register specified by the ModRM reg field.128-bit XMM register specified by the ModRM r/m field.The ModRM mod field must be 11b.A 128-bit XMM register or memory operand specified bythe ModRM byte. Memory addresses can be computedfrom a segment register, SIB byte, and/or displacement.A memory operand addressed by the DS.rSI registers. Usedin string instructions.A memory operand addressed by the ES.rDI registers.Used in string instructions.Two 16-bit or 32-bit memory operands, depending on theeffective operand size. Used in the BOUND instruction.A byte, irrespective of the effective operand size.A doubleword (32 bits), irrespective of the effectiveoperand size.A double-quadword (128 bits), irrespective of the effectiveoperand size.A 32-bit or 48-bit far pointer, depending on the effectiveoperand size.A 128-bit double-precision floating-point vector operand(packed double).A 64-bit MMX operand (packed integer).A 128-bit single-precision floating-point vector operand(packed single).A quadword, irrespective of the effective operand size.A 6-byte or 10-byte pseudo-descriptor.A scalar double-precision floating-point operand (scalardouble).376 Appendix A: Opcode and Operand Encodings
24594 Rev. 3.10 February 2005 AMD64 TechnologysissvwzA scalar doubleword (32-bit) integer operand (scalarinteger).A scalar single-precision floating-point operand (scalarsingle).A word, doubleword, or quadword, depending on theeffective operand size.A word, irrespective of the effective operand size.A word if the effective operand size is 16 bits, or adoubleword if the effective operand size is 32 or 64 bits.A.2 Opcode Encodings/n A ModRM-byte reg field or SIB-byte base field that containsa value (n) between zero (binary 000) and 7 (binary 111).For definitions of the mnemonics used to name registers, see“Summary of Registers and Data Types” on page 30.A.2.1 One-ByteOpcodesTable A-1 on page 378 shows the one-byte opcodes in which thelow nibble is in the range 0–7h. Table A-2 on page 379 showsthose opcodes in which the low nibble is in the range 8–Fh. Inboth tables, the rows show the full range (0–Fh) of the highnibble, and the columns show the specified range of the lownibble.Appendix A: Opcode and Operand Encodings 377
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24594 Rev. 3.10 February 2005 AMD64 TechnologysissvwzA scalar doubleword (32-bit) integer oper<strong>and</strong> (scalarinteger).A scalar single-precision floating-point oper<strong>and</strong> (scalarsingle).A word, doubleword, or quadword, depending on theeffective oper<strong>and</strong> size.A word, irrespective of the effective oper<strong>and</strong> size.A word if the effective oper<strong>and</strong> size is 16 bits, or adoubleword if the effective oper<strong>and</strong> size is 32 or 64 bits.A.2 Opcode Encodings/n A ModRM-byte reg field or SIB-byte base field that containsa value (n) between zero (binary 000) <strong>and</strong> 7 (binary 111).For definitions of the mnemonics used to name registers, see“Summary of Registers <strong>and</strong> Data Types” on page 30.A.2.1 One-ByteOpcodesTable A-1 on page 378 shows the one-byte opcodes in which thelow nibble is in the range 0–7h. Table A-2 on page 379 showsthose opcodes in which the low nibble is in the range 8–Fh. Inboth tables, the rows show the full range (0–Fh) of the highnibble, <strong>and</strong> the columns show the specified range of the lownibble.Appendix A: Opcode <strong>and</strong> Oper<strong>and</strong> Encodings 377
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