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AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid Opcode, #UD X X X The WRMSR instruction is not supported, as indicated by EDX bit 5returned by CPUID function 1 or 8000_0001h.General protection,#GPXXXXCPL was not 0.The value in ECX specifies a reserved or unimplemented MSRaddress.XXWriting 1 to any bit that must be zero (MBZ) in the MSR.374 WRMSR
24594 Rev. 3.10 February 2005 AMD64 TechnologyAppendix AOpcode and Operand EncodingsA.1 Opcode-Syntax NotationThis section specifies the hexadecimal and/or binary encodingsfor the opcodes and the implicit operand references used in theAMD64 instruction set. For an overview of the instructionformats to which these encodings apply, see Chapter 1,“Instruction Formats.”The following notation is used in this section to specify opcodesand their operands:ACDEFGIJMOPPRQFar pointer is encoded in the instruction.Control register specified by the ModRM reg field.Debug register specified by the ModRM reg field.General purpose register or memory operand specified bythe ModRM byte. Memory addresses can be computedfrom a segment register, SIB byte, and/or displacement.rFLAGS register.General purpose register specified by the ModRM regfield.Immediate value.The instruction includes a relative offset that is added tothe rIP.A memory operand specified by the ModRM byte.The offset of an operand is encoded in the instruction.There is no ModRM byte in the instruction. Complexaddressing using the SIB byte cannot be done.64-bit MMX register specified by the ModRM reg field.64-bit MMX register specified by the ModRM r/m field.The ModRM mod field must be 11b.64-bit MMX-register or memory operand specified by theModRM byte. Memory addresses can be computed from asegment register, SIB byte, and/or displacement.Appendix A: Opcode and Operand Encodings 375
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