Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005WBINVDWriteback and Invalidate CachesThe WBINVD instruction writes all modified cache lines in the internal caches back tomain memory and invalidates (flushes) internal caches. It then causes external cachesto write back modified data to main memory; the external caches are subsequentlyinvalidated. After invalidating internal caches, the processor proceeds immediatelywith the execution of the next instruction without waiting for external hardware toinvalidate its caches.The INVD instruction can be used when cache coherence with memory is notimportant.This instruction does not invalidate TLB caches.This is a privileged instruction. The current privilege level of a procedure invalidatingthe processor’s internal caches must be zero.WBINVD is a serializing instruction.Mnemonic Opcode DescriptionWBINVD 0F 09 Write modified cache lines to main memory, invalidate internalcaches, and trigger external cache flushes.Related InstructionsCLFLUSH, INVDrFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X CPL was not 0.372 WBINVD
24594 Rev. 3.10 February 2005 AMD64 TechnologyWRMSRWrite to Model-Specific RegisterWrites data to 64-bit model-specific registers (MSRs). These registers are widely usedin performance-monitoring and debugging applications, as well as testability andprogram execution tracing.This instruction writes the contents of the EDX:EAX register pair into a 64-bit modelspecificregister specified in the ECX register. The 32 bits in the EDX register aremapped into the high-order bits of the model-specific register and the 32 bits in EAXform the low-order 32 bits.This instruction must be executed at a privilege level of 0 or a general protection fault#GP(0) will be raised. This exception is also generated if an attempt is made to specifya reserved or unimplemented model-specific register in ECX.WRMSR is a serializing instruction.The CPUID instruction can provide model information useful in determining theexistence of a particular MSR.See Volume 2, System Programming, for more information about model-specificregisters, machine check architecture, performance monitoring and debug registers.Mnemonic Opcode DescriptionWRMSR 0F 30 Write EDX:EAX to the MSR specified by ECX.Related InstructionsRDMSRrFLAGS AffectedNoneWRMSR 373
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24594 Rev. 3.10 February 2005 AMD64 TechnologyWRMSRWrite to Model-Specific RegisterWrites data to 64-bit model-specific registers (MSRs). These registers are widely usedin performance-monitoring <strong>and</strong> debugging applications, as well as testability <strong>and</strong>program execution tracing.This instruction writes the contents of the EDX:EAX register pair into a 64-bit modelspecificregister specified in the ECX register. The 32 bits in the EDX register aremapped into the high-order bits of the model-specific register <strong>and</strong> the 32 bits in EAXform the low-order 32 bits.This instruction must be executed at a privilege level of 0 or a general protection fault#GP(0) will be raised. This exception is also generated if an attempt is made to specifya reserved or unimplemented model-specific register in ECX.WRMSR is a serializing instruction.The CPUID instruction can provide model information useful in determining theexistence of a particular MSR.See <strong>Volume</strong> 2, <strong>System</strong> Programming, for more information about model-specificregisters, machine check architecture, performance monitoring <strong>and</strong> debug registers.Mnemonic Opcode DescriptionWRMSR 0F 30 Write EDX:EAX to the MSR specified by ECX.Related <strong>Instructions</strong>RDMSRrFLAGS AffectedNoneWRMSR 373
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