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AMD64 Technology 24594 Rev. 3.10 February 2005SS.sel = MSR_STAR.SYSRET_CS + 8RFLAGS.IF = 1CPL = 3// SS selector is changed.// SS base, limit, attributes unchanged.RIP = temp_RIPEXITRelated InstructionsSYSCALL, SYSENTER, SYSEXITrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFM M M M 0 M M M M M M M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsExceptionInvalid opcode, #UDRealXVirtual8086 Protected Cause of ExceptionXXThe SYSCALL and SYSRET instructions are not supported,as indicated by EDX bit 11 returned by CPUID extendedfunction 8000_0001h.General protection, #GP X XXXXXThe system call extension bit (SCE) of the extendedfeature enable register (EFER) is set to 0. (The EFERregister is MSR C000_0080h.)This instruction is only recognized in protected mode.CPL was not 0.366 SYSRET
24594 Rev. 3.10 February 2005 AMD64 TechnologyUD2Undefined OperationGenerates an invalid opcode exception. Unlike other undefined opcodes that may bedefined as legal instructions in the future, UD2 is guaranteed to stay undefined.Mnemonic Opcode DescriptionUD2 0F 0B Raise an invalid opcode exception.Related InstructionsNonerFLAGS AffectedNoneExceptionsVirtualException Real 8086 Protected Cause of ExceptionInvalid opcode, #UD X X X This instruction is not recognized.UD2 367
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