Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionsExceptionInvalid opcode, #UDRealXVirtual8086 Protected Cause of ExceptionXXThe SYSCALL and SYSRET instructions are not supported,as indicated by EDX bit 11 returned by CPUID extendedfunction 8000_0001h.XXXThe system call extension bit (SCE) of the extendedfeature enable register (EFER) is set to 0. (The EFERregister is MSR C000_0080h.)358 SYSCALL
24594 Rev. 3.10 February 2005 AMD64 TechnologySYSENTERSystem CallTransfers control to a fixed entry point in an operating system. It is designed for useby system and application software implementing a flat-segment memory model. Thisinstruction is valid only in legacy mode.Three model-specific registers (MSRs) are used to specify the target address and stackpointers for the SYSENTER instruction, as well as the CS and SS selectors of thecalled and returned procedures:• MSR_SYSENTER_CS: Contains the CS selector of the called procedure. The SSselector is set to MSR_SYSENTER_CS + 8.• MSR_SYSENTER_ESP: Contains the called procedure’s stack pointer.• MSR_SYSENTER_EIP: Contains the offset into the CS of the called procedure.The hidden portions of the CS and SS segment registers are not loaded from thedescriptor table as they would be using a legacy x86 CALL instruction. Instead, thehidden portions are forced by the processor to the following values:• The CS and SS base values are forced to 0.• The CS and SS limit values are forced to 4 Gbytes.• The CS segment attributes are set to execute/read 32-bit code with a CPL of zero.• The SS segment attributes are set to read/write and expand-up with a 32-bit stackreferenced by ESP.System software must create corresponding descriptor-table entries referenced by thenew CS and SS selectors that match the values described above.The return EIP and application stack are not saved by this instruction. Systemsoftware must explicitly save that information.An invalid-opcode exception occurs if this instruction is used in long mode. Softwareshould use the SYSCALL (and SYSRET) instructions in long mode. If SYSENTER isused in real mode, a #GP is raised.For additional information on this instruction, see “SYSENTER and SYSEXIT(Legacy Mode Only)” in Volume 2.Mnemonic Opcode DescriptionSYSENTER 0F 34 Call operating system.SYSENTER 359
- Page 338 and 339: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 340 and 341: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 342 and 343: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 344 and 345: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 346 and 347: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 348 and 349: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 350 and 351: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 352 and 353: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 354 and 355: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 356 and 357: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 358 and 359: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 360 and 361: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 362 and 363: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 364 and 365: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 366 and 367: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 368 and 369: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 370 and 371: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 372 and 373: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 374 and 375: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 376 and 377: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 378 and 379: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 380 and 381: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 382 and 383: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 384 and 385: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 386 and 387: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 390 and 391: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 392 and 393: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 394 and 395: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 396 and 397: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 398 and 399: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 400 and 401: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 402 and 403: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 404 and 405: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 406 and 407: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 408 and 409: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 410 and 411: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 412 and 413: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 414 and 415: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 416 and 417: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 418 and 419: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 420 and 421: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 422 and 423: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 424 and 425: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 426 and 427: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 428 and 429: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 430 and 431: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 432 and 433: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 434 and 435: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 436 and 437: AMD64 Technology 24594 Rev. 3.10 Fe
AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionsExceptionInvalid opcode, #UDRealXVirtual8086 Protected Cause of ExceptionXXThe SYSCALL <strong>and</strong> SYSRET instructions are not supported,as indicated by EDX bit 11 returned by CPUID extendedfunction 8000_0001h.XXXThe system call extension bit (SCE) of the extendedfeature enable register (EFER) is set to 0. (The EFERregister is MSR C000_0080h.)358 SYSCALL
Change language