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AMD64 Technology 24594 Rev. 3.10 February 2005STRStore Task RegisterStores the task register (TR) selector to a register or memory destination operand.If the destination is a register, the selector is zero-extended into a 16-, 32-, or 64-bitgeneral purpose register, depending on the operand size.If the destination is a memory location, the segment selector is written to memory as a16-bit value, regardless of operand size.The STR instruction can only be used in protected mode, but it can be used at anyprivilege level.Mnemonic Opcode DescriptionSTR reg16 0F 00 /1 Store the segment selector from the task register to a 16-bit generalpurposeregister.STR reg32 0F 00 /1 Store the segment selector from the task register to a 32-bit generalpurposeregister.STR reg64 0F 00 /1 Store the segment selector from the task register to a 64-bit generalpurposeregister.STR mem16 0F 00 /1 Store the segment selector from the task register to a 16-bit memorylocation.Related InstructionsLGDT, LIDT, LLDT, LTR, SIDT, SGDT, SLDTrFLAGS AffectedNone350 STR
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X This instruction is only recognized in protected mode.Stack, #SS X A memory address exceeded the stack segment limit or was noncanonical.General protection, #GPX A memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X A page fault resulted from the execution of the instruction.Alignment check, #AC X An unaligned memory reference was performed while alignmentchecking was enabled.STR 351
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