Volume 3: General-Purpose and System Instructions - Stanford ...

AMD64 Technology 24594 Rev. 3.10 February 2005Certain instructions reference pointer registers or countregisters implicitly, rather than explicitly. In such instructions,the address-size prefix affects the size of such addressing andcount registers, just as it does when such registers are explicitlyreferenced. Table 1-4 lists all such instructions and the registersreferenced using the three possible address sizes.Table 1-4.Pointer and Count Registers and the Address-Size PrefixInstructionCMPS, CMPSB, CMPSW,CMPSD, CMPSQ—CompareStringsINS, INSB, INSW, INSD—InputStringJCXZ, JECXZ, JRCXZ—Jump onCX/ECX/RCX ZeroLODS, LODSB, LODSW,LODSD, LODSQ—Load StringLOOP, LOOPE, LOOPNZ,LOOPNE, LOOPZ—LoopMOVS, MOVSB, MOVSW,MOVSD, MOVSQ—Move StringOUTS, OUTSB, OUTSW,OUTSD—Output StringREP, REPE, REPNE, REPNZ,REPZ—Repeat PrefixesSCAS, SCASB, SCASW, SCASD,SCASQ—Scan StringSTOS, STOSB, STOSW, STOSD,STOSQ—Store StringXLAT, XLATB—Table Look-upTranslation16-BitAddress SizePointer or Count Register32-BitAddress Size64-BitAddress SizeSI, DI, CX ESI, EDI, ECX RSI, RDI, RCXDI, CX EDI, ECX RDI, RCXCX ECX RCXSI, CX ESI, ECX RSI, RCXCX ECX RCXSI, DI, CX ESI, EDI, ECX RSI, RDI, RCXSI, CX ESI, ECX RSI, RCXCX ECX RCXDI, CX EDI, ECX RDI, RCXDI, CX EDI, ECX RDI, RCXBX EBX RBX8 Chapter 1: Instruction Formats