Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005STISet Interrupt FlagSets the interrupt flag (IF) in the rFLAGS register to 1, thereby allowing externalinterrupts received on the INTR input. Interrupts received on the non-maskableinterrupt (NMI) input are not affected by this instruction.In real mode, this instruction sets IF to 1.In protected mode and virtual-8086-mode, this instruction is IOPL-sensitive. If theCPL is less than or equal to the rFLAGS.IOPL field, the instruction sets IF to 1.In protected mode, if IOPL < 3, CPL = 3, and protected mode virtual interrupts areenabled (CR4.PVI = 1), then the instruction instead sets rFLAGS.VIF to 1. If none ofthese conditions apply, the processor raises a general protection exception (#GP). Formore information, see “Protected Mode Virtual Interrupts” in Volume 2.In virtual-8086 mode, if IOPL < 3 and the virtual-8086-mode extensions are enabled(CR4.VME = 1), the STI instruction instead sets the virtual interrupt flag(rFLAGS.VIF) to 1.If STI sets the IF flag and IF was initially clear, then interrupts are not enabled untilafter the instruction following STI. Thus, if IF is 0, this code will not allow an INTR tohappen:STICLIIn the following sequence, INTR will be allowed to happen only after the NOP.STINOPCLIIf STI sets the VIF flag and VIP is already set, a #GP fault will be generated.See “Virtual-8086 Mode Extensions” in Volume 2 for more information about IOPLsensitiveinstructions.Mnemonic Opcode DescriptionSTI FB Set interrupt flag (IF) to 1.348 STI
24594 Rev. 3.10 February 2005 AMD64 TechnologyActionIF (CPL
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24594 Rev. 3.10 February 2005 AMD64 TechnologyActionIF (CPL
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