Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologySMSWStore Machine Status WordStores the lower bits of the machine status word (CR0). The target can be a 16-, 32-, or64-bit register or a 16-bit memory operand.This instruction is provided for compatibility with early processors.This instruction can be used at any privilege level (CPL).Mnemonic Opcode DescriptionSMSW reg16 0F 01 /4 Store the low 16 bits of CR0 to a 16-bit register.SMSW reg32 0F 01 /4 Store the low 32 bits of CR0 to a 32-bit register.SMSW reg64 0F 01 /4 Store the entire 64-bit CR0 to a 64-bit register.SMSW mem16 0F 01 /4 Store the low 16 bits of CR0 to memory.Related InstructionsLMSW, MOV(CRn)rFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.SMSW 347