Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X XA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.342 SGDT
24594 Rev. 3.10 February 2005 AMD64 TechnologySIDTStore Interrupt Descriptor Table RegisterStores the interrupt descriptor table register (IDTR) in the destination operand. Inlegacy and compatibility mode, the destination operand is 6 bytes; in 64-bit mode it is10 bytes. In all modes, operand-size prefixes are ignored.In non-64-bit mode, the lower two bytes of the operand specify the 16-bit limit and theupper 4 bytes specify the 32-bit base address.In 64-bit mode, the lower two bytes of the operand specify the 16-bit limit and theupper 8 bytes specify the 64-bit base address.This instruction is intended for use in operating system software, but it can be used atany privilege level.Mnemonic Opcode DescriptionSIDT mem16:32 0F 01 /1 Store interrupt descriptor table register to memory.SIDT mem16:64 0F 01 /1 Store interrupt descriptor table register to memory.Related InstructionsSGDT, SLDT, STR, LGDT, LIDT, LLDT, LTRrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The operand was a register.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.SIDT 343
- Page 322 and 323: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 324 and 325: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 326 and 327: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 328 and 329: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 330 and 331: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 332 and 333: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 334 and 335: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 336 and 337: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 338 and 339: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 340 and 341: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 342 and 343: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 344 and 345: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 346 and 347: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 348 and 349: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 350 and 351: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 352 and 353: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 354 and 355: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 356 and 357: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 358 and 359: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 360 and 361: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 362 and 363: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 364 and 365: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 366 and 367: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 368 and 369: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 370 and 371: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 374 and 375: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 376 and 377: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 378 and 379: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 380 and 381: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 382 and 383: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 384 and 385: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 386 and 387: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 388 and 389: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 390 and 391: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 392 and 393: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 394 and 395: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 396 and 397: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 398 and 399: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 400 and 401: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 402 and 403: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 404 and 405: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 406 and 407: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 408 and 409: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 410 and 411: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 412 and 413: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 414 and 415: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 416 and 417: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 418 and 419: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 420 and 421: AMD64 Technology 24594 Rev. 3.10 Fe
AMD64 Technology 24594 Rev. 3.10 February 2005Exception<strong>General</strong> protection,#GPRealVirtual8086 Protected Cause of ExceptionX X XA memory address exceeded a data segment limit or was noncanonical.XThe destination oper<strong>and</strong> was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.342 SGDT
Change language