Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedAll flags are restored from the state-save map (SSM).ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFM M M M M M M M M M M M M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsVirtualException Real 8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The processor was not in System Management Mode (SMM).340 RSM
24594 Rev. 3.10 February 2005 AMD64 TechnologySGDTStore Global Descriptor Table RegisterStores the global descriptor table register (GDTR) into the destination operand. Inlegacy and compatibility mode, the destination operand is six bytes; in 64-bit mode, itis 10 bytes. In all modes, operand-size prefixes are ignored.In non-64-bit mode, the lower two bytes of the operand specify the 16-bit limit and theupper 4 bytes specify the 32-bit base address.In 64-bit mode, the lower two bytes of the operand specify the 16-bit limit and theupper 8 bytes specify the 64-bit base address.This instruction is intended for use in operating system software, but it can be used atany privilege level.Mnemonic Opcode DescriptionSGDT mem16:32 0F 01 /0 Store global descriptor table register to memory.SGDT mem16:64 0F 01 /0 Store global descriptor table register to memory.Related InstructionsSIDT, SLDT, STR, LGDT, LIDT, LLDT, LTRrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The operand was a register.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.SGDT 341
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24594 Rev. 3.10 February 2005 AMD64 TechnologySGDTStore Global Descriptor Table RegisterStores the global descriptor table register (GDTR) into the destination oper<strong>and</strong>. Inlegacy <strong>and</strong> compatibility mode, the destination oper<strong>and</strong> is six bytes; in 64-bit mode, itis 10 bytes. In all modes, oper<strong>and</strong>-size prefixes are ignored.In non-64-bit mode, the lower two bytes of the oper<strong>and</strong> specify the 16-bit limit <strong>and</strong> theupper 4 bytes specify the 32-bit base address.In 64-bit mode, the lower two bytes of the oper<strong>and</strong> specify the 16-bit limit <strong>and</strong> theupper 8 bytes specify the 64-bit base address.This instruction is intended for use in operating system software, but it can be used atany privilege level.Mnemonic Opcode DescriptionSGDT mem16:32 0F 01 /0 Store global descriptor table register to memory.SGDT mem16:64 0F 01 /0 Store global descriptor table register to memory.Related <strong>Instructions</strong>SIDT, SLDT, STR, LGDT, LIDT, LLDT, LTRrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The oper<strong>and</strong> was a register.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.SGDT 341
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