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AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The RDTSCP instruction is not supported, as indicated by EDX bit 27returned by CPUID extended function 8000_0001h.General protection, #GP X X CPL was not 0 and CR4.TSD = 1.338 RDTSCP
24594 Rev. 3.10 February 2005 AMD64 TechnologyRSMResume from System Management ModeResumes an operating system or application procedure previously interrupted by asystem management interrupt (SMI). The processor state is restored from theinformation saved when the SMI was taken. If the processor detects invalid stateinformation in the system management mode (SMM) save area during RSM, it goesinto a shutdown state.RSM will shutdown if any of the following conditions are found in the save map (SSM):• An illegal combination of flags in CR0 (CR0.PG = 1 and CR0.PE = 0, or CR0.NW =1 and CR0.CD = 0).• A reserved bit in CR0, CR3, CR4, DR6, DR7, or the extended feature enable register(EFER) is set to 1.• The following bit combination occurs: EFER.LME = 1, CR0.PG = 1, CR4.PAE = 0.• The following bit combination occurs: EFER.LME = 1, CR0.PG = 1, CR4.PAE = 1,CS.D = 1, CS.L = 1.• SMM revision field has been modified.The AMD64 architecture uses a new 64-bit SMM state-save memory image. This 64-bitsave-state map is used in all modes, regardless of mode. See “System-ManagementMode” in Volume 2 for details.Mnemonic Opcode DescriptionRSM 0F AA Resume operation of an interrupted program.Related InstructionsNoneRSM 339
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