Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005RDTSCRead Time-Stamp CounterLoads the value of the processor’s 64-bit time-stamp counter into registers EDX:EAX.The time-stamp counter is contained in a 64-bit model-specific register (MSR). Theprocessor sets the counter to 0 upon reset and increments the counter every clockcycle. INIT does not modify the TSC.The high-order 32 bits are loaded into EDX, and the low-order 32 bits are loaded intothe EAX register. This instruction ignores operand size.When the time-stamp disable flag (TSD) in CR4 is set to 1, the RDTSC instruction canonly be used at privilege level 0. If the TSD flag is 0, this instruction can be used at anyprivilege level.This instruction is not serializing. Therefore, there is no guarantee that all instructionshave completed at the time the time-stamp counter is read.Mnemonic Opcode DescriptionRDTSC 0F 31 Copy the time-stamp counter into EDX:EAX.Related InstructionsRDTSCP, RDMSR, WRMSRrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The RDTSC instruction is not supported, as indicated by EDX bit 4returned by CPUID standard function 1 or extended function8000_0001h.General protection, #GP X X CPL was not 0 and CR4.TSD = 1.336 RDTSC
24594 Rev. 3.10 February 2005 AMD64 TechnologyRDTSCPRead Time-Stamp Counter and Processor IDLoads the value of the processor’s 64-bit time-stamp counter into registers EDX:EAX,and loads the value of TSC_AUX into ECX. This instruction ignores operand size.The time-stamp counter is contained in a 64-bit model-specific register (MSR). Theprocessor sets the counter to 0 upon reset and increments the counter every clockcycle. INIT does not modify the TSC.The high-order 32 bits are loaded into EDX, and the low-order 32 bits are loaded intothe EAX register.The TSC_AUX value is contained in the low-order 32 bits of the TSC_AUX register(MSR address C000_0103h). This MSR is initialized by privileged software to anymeaningful value, such as a processor ID, that software wants to associate with thereturned TSC value.When the time-stamp disable flag (TSD) in CR4 is set to 1, the RDTSCP instructioncan only be used at privilege level 0. If the TSD flag is 0, this instruction can be used atany privilege level.Unlike the RDTSC instruction, RDTSCP is a serializing instruction.Use the CPUID instruction to verify support for this instruction.Mnemonic Opcode DescriptionRDTSC P 0F 01 F9 Copy the time-stamp counter into EDX:EAX. and theTSC_AUX register into ECX.Related InstructionsRDTSCrFLAGS AffectedNoneRDTSCP 337
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AMD64 Technology 24594 Rev. 3.10 February 2005RDTSCRead Time-Stamp CounterLoads the value of the processor’s 64-bit time-stamp counter into registers EDX:EAX.The time-stamp counter is contained in a 64-bit model-specific register (MSR). Theprocessor sets the counter to 0 upon reset <strong>and</strong> increments the counter every clockcycle. INIT does not modify the TSC.The high-order 32 bits are loaded into EDX, <strong>and</strong> the low-order 32 bits are loaded intothe EAX register. This instruction ignores oper<strong>and</strong> size.When the time-stamp disable flag (TSD) in CR4 is set to 1, the RDTSC instruction canonly be used at privilege level 0. If the TSD flag is 0, this instruction can be used at anyprivilege level.This instruction is not serializing. Therefore, there is no guarantee that all instructionshave completed at the time the time-stamp counter is read.Mnemonic Opcode DescriptionRDTSC 0F 31 Copy the time-stamp counter into EDX:EAX.Related <strong>Instructions</strong>RDTSCP, RDMSR, WRMSRrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The RDTSC instruction is not supported, as indicated by EDX bit 4returned by CPUID st<strong>and</strong>ard function 1 or extended function8000_0001h.<strong>General</strong> protection, #GP X X CPL was not 0 <strong>and</strong> CR4.TSD = 1.336 RDTSC
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