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AMD64 Technology 24594 Rev. 3.10 February 2005RDPMCRead Performance-Monitoring CounterLoads the contents of a 64-bit performance counter register (PerfCtrn) specified inthe ECX register into registers EDX:EAX. The EDX register receives the high-order32 bits and the EAX register receives the low order 32 bits. The RDPMC instructionignores operand size; ECX always holds the number of the PerfCtr, and EDX:EAXholds the data.The AMD64 architecture currently supports four performance counters: PerfCtr0through PerfCtr3. To specify the performance counter number in ECX, specify thecounter number (0000_0000h–0000_0003h), rather than the performance counterMSR address (C001_0004h–C001_0007h).Programs running at any privilege level can read performance monitor counters if thePCE flag in CR4 is set to 1; otherwise this instruction must be executed at a privilegelevel of 0.This instruction is not serializing. Therefore, there is no guarantee that all instructionshave completed at the time the performance counter is read.For more information about performance-counter registers, see the documentation forvarious hardware implementations and “Performance Counters” in Volume 2.Mnemonic Opcode DescriptionRDPMC 0F 33 Copy the performance monitor counter specified by ECXinto EDX:EAX.Related InstructionsRDMSR, WRMSRrFLAGS AffectedNone334 RDPMC
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionsExceptionGeneral Protection,#GPRealXVirtual8086 Protected Cause of ExceptionXXThe value in ECX specified an unimplemented performance counternumber.XXCPL was not 0 and CR4.PCE = 0.RDPMC 335
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