Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Related InstructionsCLTS, LMSW, SMSWrFLAGS AffectedNoneExceptionsExceptionInvalid Instruction,#UDGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X X An illegal control register was referenced (CR1, CR5–CR7,CR9–CR15).XXXXCPL was not 0.An attempt was made to set CR0.PG = 1 and CR0.PE = 0.XXXXXXXXXAn attempt was made to set CR0.CD = 0 and CR0.NW = 1.Reserved bits were set in the page-directory pointers table (used inthe legacy extended physical addressing mode) and the instructionmodified CR0, CR3, or CR4.An attempt was made to write 1 to any reserved bit in CR0, CR3, CR4or CR8.An attempt was made to set CR0.PG while long mode was enabled(EFER.LME = 1), but paging address extensions were disabled(CR4.PAE = 0).An attempt was made to clear CR4.PAE while long mode was active(EFER.LMA = 1).330 MOV(CRn)
24594 Rev. 3.10 February 2005 AMD64 TechnologyMOV(DRn)Move to/from Debug RegistersMoves the contents of a debug register into a 32-bit or 64-bit general-purpose registeror vice versa.In 64-bit mode, the operand size is fixed at 64 bits without the need for a REX prefix.In non-64-bit mode, the operand size is fixed at 32-bits and the upper 32 bits of thedestination are forced to 0.DR0 through DR3 are linear breakpoint address registers. DR6 is the debug statusregister and DR7 is the debug control register. DR4 and DR5 are aliased to DR6 andDR7 if CR4.DE = 0, and are reserved if CR4.DE = 1.DR8 through DR15 are reserved and generate an undefined opcode exception ifreferenced.These instructions are privileged and must be executed at CPL 0.The MOV DRn,reg32 and MOV DRn,reg64 instructions are serializing instructions.The MOV(DR) instruction is always treated as a register-to-register (MOD = 11)instruction, regardless of the encoding of the MOD field in the MODR/M byte.See “Debug and Performance Resources” in Volume 2 for details.Mnemonic Opcode DescriptionMOV reg32, DRn 0F 21 /r Move the contents of DRn to a 32-bit register.MOV reg64, DRn 0F 21 /r Move the contents of DRn to a 64-bit register.MOV DRn, reg32 0F 23 /r Move the contents of a 32-bit register to DRn.MOV DRn, reg64 0F 23 /r Move the contents of a 64-bit register to DRn.Related InstructionsNonerFLAGS AffectedNoneMOV(DRn) 331
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24594 Rev. 3.10 February 2005 AMD64 TechnologyMOV(DRn)Move to/from Debug RegistersMoves the contents of a debug register into a 32-bit or 64-bit general-purpose registeror vice versa.In 64-bit mode, the oper<strong>and</strong> size is fixed at 64 bits without the need for a REX prefix.In non-64-bit mode, the oper<strong>and</strong> size is fixed at 32-bits <strong>and</strong> the upper 32 bits of thedestination are forced to 0.DR0 through DR3 are linear breakpoint address registers. DR6 is the debug statusregister <strong>and</strong> DR7 is the debug control register. DR4 <strong>and</strong> DR5 are aliased to DR6 <strong>and</strong>DR7 if CR4.DE = 0, <strong>and</strong> are reserved if CR4.DE = 1.DR8 through DR15 are reserved <strong>and</strong> generate an undefined opcode exception ifreferenced.These instructions are privileged <strong>and</strong> must be executed at CPL 0.The MOV DRn,reg32 <strong>and</strong> MOV DRn,reg64 instructions are serializing instructions.The MOV(DR) instruction is always treated as a register-to-register (MOD = 11)instruction, regardless of the encoding of the MOD field in the MODR/M byte.See “Debug <strong>and</strong> Performance Resources” in <strong>Volume</strong> 2 for details.Mnemonic Opcode DescriptionMOV reg32, DRn 0F 21 /r Move the contents of DRn to a 32-bit register.MOV reg64, DRn 0F 21 /r Move the contents of DRn to a 64-bit register.MOV DRn, reg32 0F 23 /r Move the contents of a 32-bit register to DRn.MOV DRn, reg64 0F 23 /r Move the contents of a 64-bit register to DRn.Related <strong>Instructions</strong>NonerFLAGS AffectedNoneMOV(DRn) 331
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