Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 200516 bits of the 32-bit adjusted segment limit and loads the lower 16-bits into the targetregister.Mnemonic Opcode DescriptionLSL reg16, reg/mem16 0F 03 /r Loads a 16-bit general-purpose register with the segment limit for aselector specified in a 16-bit memory or register operand.LSL reg32, reg/mem16 0F 03 /r Loads a 32-bit general-purpose register with the segment limit for aselector specified in a 16-bit memory or register operand.LSL reg64, reg/mem16 0F 03 /r Loads a 64-bit general-purpose register with the segment limit for aselector specified in a 16-bit memory or register operand.Related InstructionsARPL, LAR, VERR, VERWrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X This instruction is only recognized in protected mode.Stack, #SS X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPXA memory address exceeded a data segment limit or was noncanonical.MXA null data segment was used to reference memory.X The extended attribute bits of a system descriptor was not zero in 64-bit modePage fault, #PF X A page fault resulted from the execution of the instruction.Alignment check, #AC X An unaligned memory reference was performed while alignmentchecking was enabled.326 LSL
24594 Rev. 3.10 February 2005 AMD64 TechnologyLTRLoad Task RegisterLoads the specified segment selector into the visible portion of the task register (TR).The processor uses the selector to locate the descriptor for the TSS in the globaldescriptor table. It then loads this descriptor into the hidden portion of TR. The TSSdescriptor in the GDT is marked busy, but no task switch is made.If the source operand is null, a general protection exception (#GP) is generated.In legacy and compatibility modes, the TSS descriptor is 8 bytes long and contains a32-bit base address.In 64-bit mode, the instruction references a 64-bit descriptor to load a 64-bit baseaddress. The TSS type (09H) is redefined in 64-bit mode for use as the 16-byte TSSdescriptor.This instruction must be executed in protected mode when the current privilege levelis 0. It is only provided for use by operating system software.The operand size attribute has no effect on this instruction.LTR is a serializing instruction.Mnemonic Opcode DescriptionLTR reg/mem16 0F 00 /3 Load the 16-bit segment selector into the task register and load the TSSdescriptor from the GDT.Related InstructionsLGDT, LIDT, LLDT, STR, SGDT, SIDT, SLDTrFLAGS AffectedNoneLTR 327
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AMD64 Technology 24594 Rev. 3.10 February 200516 bits of the 32-bit adjusted segment limit <strong>and</strong> loads the lower 16-bits into the targetregister.Mnemonic Opcode DescriptionLSL reg16, reg/mem16 0F 03 /r Loads a 16-bit general-purpose register with the segment limit for aselector specified in a 16-bit memory or register oper<strong>and</strong>.LSL reg32, reg/mem16 0F 03 /r Loads a 32-bit general-purpose register with the segment limit for aselector specified in a 16-bit memory or register oper<strong>and</strong>.LSL reg64, reg/mem16 0F 03 /r Loads a 64-bit general-purpose register with the segment limit for aselector specified in a 16-bit memory or register oper<strong>and</strong>.Related <strong>Instructions</strong>ARPL, LAR, VERR, VERWrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X This instruction is only recognized in protected mode.Stack, #SS X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPXA memory address exceeded a data segment limit or was noncanonical.MXA null data segment was used to reference memory.X The extended attribute bits of a system descriptor was not zero in 64-bit modePage fault, #PF X A page fault resulted from the execution of the instruction.Alignment check, #AC X An unaligned memory reference was performed while alignmentchecking was enabled.326 LSL
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