Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005LMSWLoad Machine Status WordLoads the lower four bits of the 16-bit register or memory operand into bits 3–0 of themachine status word in register CR0. Only the protection enabled (PE), monitorcoprocessor (MP), emulation (EM), and task switched (TS) bits of CR0 are modified.Additionally, LMSW can set CR0.PE, but cannot clear it.The LMSW instruction can be used only when the current privilege level is 0. It is onlyprovided for compatibility with early processors.Use the MOV CR0 instruction to load all 32 or 64 bits of CR0.Mnemonic Opcode DescriptionLMSW reg/mem16 0F 01 /6 Load the lower 4 bits of the source into the lower 4 bits of CR0.Related InstructionsMOV (CRn), SMSWrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPXXA memory address exceeded a data segment limit or was noncanonical.XXCPL was not 0.X A null data segment was used to reference memory.Page fault, #PF X A page fault resulted from the execution of the instruction.324 LMSW
24594 Rev. 3.10 February 2005 AMD64 TechnologyLSLLoad Segment LimitLoads the segment limit from the segment descriptor specified by a 16-bit sourceregister or memory operand into a specified 16-bit, 32-bit, or 64-bit general-purposeregister and sets the zero (ZF) flag in the rFLAGS register if successful. LSL clears thezero flag if the descriptor is invalid for any reason.In 64-bit mode, for both 32-bit and 64-bit operand sizes, 32-bit register results are zeroextendedto 64 bits.The LSL instruction checks that:• the segment selector is not a null selector.• the descriptor is within the GDT or LDT limit.• the descriptor DPL is greater than or equal to both the CPL and RPL, or the segmentis a conforming code segment.• the descriptor type is valid for the LAR instruction. Valid descriptor types areshown in the following table. LDT and TSS descriptors in 64-bit mode are onlyvalid if bits 12–8 of doubleword +12 are zero, as shown on page 111 of vol. 2 in Figure4-22.Valid Descriptor TypeDescriptionLegacy ModeLong Mode— — All code and data descriptors1 — Available 16-bit TSS2 2 LDT3 — Busy 16-bit TSS9 9 Available 32-bit or 64-bit TSSB B Busy 32-bit or 64-bit TSSIf the segment selector passes these checks and the segment limit is loaded into thedestination general-purpose register, the instruction sets the zero flag of the rFLAGSregister to 1. If the selector does not pass the checks, then LSL clears the zero flag to 0and does not modify the destination.The instruction calculates the segment limit to 32 bits, taking the 20-bit limit and thegranularity bit into account. When the operand size is 16 bits, it truncates the upperLSL 325
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24594 Rev. 3.10 February 2005 AMD64 TechnologyLSLLoad Segment LimitLoads the segment limit from the segment descriptor specified by a 16-bit sourceregister or memory oper<strong>and</strong> into a specified 16-bit, 32-bit, or 64-bit general-purposeregister <strong>and</strong> sets the zero (ZF) flag in the rFLAGS register if successful. LSL clears thezero flag if the descriptor is invalid for any reason.In 64-bit mode, for both 32-bit <strong>and</strong> 64-bit oper<strong>and</strong> sizes, 32-bit register results are zeroextendedto 64 bits.The LSL instruction checks that:• the segment selector is not a null selector.• the descriptor is within the GDT or LDT limit.• the descriptor DPL is greater than or equal to both the CPL <strong>and</strong> RPL, or the segmentis a conforming code segment.• the descriptor type is valid for the LAR instruction. Valid descriptor types areshown in the following table. LDT <strong>and</strong> TSS descriptors in 64-bit mode are onlyvalid if bits 12–8 of doubleword +12 are zero, as shown on page 111 of vol. 2 in Figure4-22.Valid Descriptor TypeDescriptionLegacy ModeLong Mode— — All code <strong>and</strong> data descriptors1 — Available 16-bit TSS2 2 LDT3 — Busy 16-bit TSS9 9 Available 32-bit or 64-bit TSSB B Busy 32-bit or 64-bit TSSIf the segment selector passes these checks <strong>and</strong> the segment limit is loaded into thedestination general-purpose register, the instruction sets the zero flag of the rFLAGSregister to 1. If the selector does not pass the checks, then LSL clears the zero flag to 0<strong>and</strong> does not modify the destination.The instruction calculates the segment limit to 32 bits, taking the 20-bit limit <strong>and</strong> thegranularity bit into account. When the oper<strong>and</strong> size is 16 bits, it truncates the upperLSL 325
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