Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005LGDTLoad Global Descriptor Table RegisterLoads the pseudo-descriptor specified by the source operand into the globaldescriptor table register (GDTR). The pseudo-descriptor is a memory locationcontaining the GDTR base and limit. In legacy and compatibility mode, the pseudodescriptoris 6 bytes; in 64-bit mode, it is 10 bytes.If the operand size is 16 bits, the high-order byte of the 6-byte pseudo-descriptor is notused. The lower two bytes specify the 16-bit limit and the third, fourth, and fifth bytesspecify the 24-bit base address. The high-order byte of the GDTR is filled with zeros.If the operand size is 32 bits, the lower two bytes specify the 16-bit limit and the upperfour bytes specify a 32-bit base address.In 64-bit mode, the lower two bytes specify the 16-bit limit and the upper eight bytesspecify a 64-bit base address. In 64-bit mode, operand-size prefixes are ignored andthe operand size is forced to 64-bits; therefore, the pseudo-descriptor is always 10bytes.This instruction is only used in operating system software and must be executed atCPL 0. It is typically executed once in real mode to initialize the processor beforeswitching to protected mode.LGDT is a serializing instruction.Mnemonic Opcode DescriptionLGDT mem16:32 0F 01 /2 Loads mem16:32 into the global descriptor table register.LGDT mem16:64 0F 01 /2 Loads mem16:64 into the global descriptor table register.Related InstructionsLIDT, LLDT, LTR, SGDT, SIDT, SLDT, STRrFLAGS AffectedNone318 LGDT
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The operand was a register.Stack, #SS X X A memory address exceeded the stack segment limit or was noncanonical.General protection, #GP XX A memory address exceeded the data segment limit or was noncanonical.XXXCPL was not 0.The new GDT base address was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X A page fault resulted from the execution of the instruction.LGDT 319
- Page 298 and 299: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 300 and 301: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 302 and 303: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 304 and 305: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 306 and 307: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 308 and 309: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 310 and 311: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 312 and 313: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 314 and 315: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 316 and 317: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 318 and 319: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 320 and 321: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 322 and 323: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 324 and 325: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 326 and 327: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 328 and 329: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 330 and 331: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 332 and 333: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 334 and 335: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 336 and 337: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 338 and 339: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 340 and 341: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 342 and 343: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 344 and 345: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 346 and 347: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 350 and 351: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 352 and 353: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 354 and 355: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 356 and 357: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 358 and 359: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 360 and 361: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 362 and 363: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 364 and 365: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 366 and 367: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 368 and 369: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 370 and 371: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 372 and 373: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 374 and 375: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 376 and 377: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 378 and 379: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 380 and 381: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 382 and 383: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 384 and 385: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 386 and 387: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 388 and 389: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 390 and 391: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 392 and 393: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 394 and 395: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 396 and 397: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The oper<strong>and</strong> was a register.Stack, #SS X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection, #GP XX A memory address exceeded the data segment limit or was noncanonical.XXXCPL was not 0.The new GDT base address was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X A page fault resulted from the execution of the instruction.LGDT 319
Change language