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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005LGDTLoad Global Descriptor Table RegisterLoads the pseudo-descriptor specified by the source oper<strong>and</strong> into the globaldescriptor table register (GDTR). The pseudo-descriptor is a memory locationcontaining the GDTR base <strong>and</strong> limit. In legacy <strong>and</strong> compatibility mode, the pseudodescriptoris 6 bytes; in 64-bit mode, it is 10 bytes.If the oper<strong>and</strong> size is 16 bits, the high-order byte of the 6-byte pseudo-descriptor is notused. The lower two bytes specify the 16-bit limit <strong>and</strong> the third, fourth, <strong>and</strong> fifth bytesspecify the 24-bit base address. The high-order byte of the GDTR is filled with zeros.If the oper<strong>and</strong> size is 32 bits, the lower two bytes specify the 16-bit limit <strong>and</strong> the upperfour bytes specify a 32-bit base address.In 64-bit mode, the lower two bytes specify the 16-bit limit <strong>and</strong> the upper eight bytesspecify a 64-bit base address. In 64-bit mode, oper<strong>and</strong>-size prefixes are ignored <strong>and</strong>the oper<strong>and</strong> size is forced to 64-bits; therefore, the pseudo-descriptor is always 10bytes.This instruction is only used in operating system software <strong>and</strong> must be executed atCPL 0. It is typically executed once in real mode to initialize the processor beforeswitching to protected mode.LGDT is a serializing instruction.Mnemonic Opcode DescriptionLGDT mem16:32 0F 01 /2 Loads mem16:32 into the global descriptor table register.LGDT mem16:64 0F 01 /2 Loads mem16:64 into the global descriptor table register.Related <strong>Instructions</strong>LIDT, LLDT, LTR, SGDT, SIDT, SLDT, STRrFLAGS AffectedNone318 LGDT

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