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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005When the oper<strong>and</strong> size is 32 or 64 bits, access rights include the DPL <strong>and</strong> type as wellas the descriptor type (S field), segment present (P flag), available to system (AVLflag), default operation size (D/B flag), <strong>and</strong> granularity flags located in bytes 4–7 of thedescriptor. Before being loaded into the destination oper<strong>and</strong>, the doubleword ismasked with 00FF_FF00H.In 64-bit mode, for both 32-bit <strong>and</strong> 64-bit oper<strong>and</strong> sizes, 32-bit register results are zeroextendedto 64 bits.This instruction can only be executed in protected mode.Mnemonic Opcode DescriptionLAR reg16, reg/mem16 0F 02 /r Reads the GDT/LDT descriptor referenced by the 16-bit sourceoper<strong>and</strong>, masks the attributes with FF00h <strong>and</strong> saves the result in the16-bit destination register.LAR reg32, reg/mem16 0F 02 /r Reads the GDT/LDT descriptor referenced by the 16-bit sourceoper<strong>and</strong>, masks the attributes with 00FFFF00h <strong>and</strong> saves the result inthe 32-bit destination register.LAR reg64, reg/mem16 0F 02 /r Reads the GDT/LDT descriptor referenced by the 16-bit sourceoper<strong>and</strong>, masks the attributes with 00FFFF00h <strong>and</strong> saves the result inthe 64-bit destination register.Related <strong>Instructions</strong>ARPL, LSL, VERR, VERWrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to one or zero is M (modified). Unaffected flags are blank. Undefined flagsare U.M316 LAR

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