Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005IRET_PROTECTEDELSE // (VIRTUAL_MODE)IRET_VIRTUALIRET_REAL:POP.v temp_RIPPOP.v temp_CSPOP.v temp_RFLAGSIF (temp_RIP > CS.limit)EXCEPTION [#GP(0)]CS.sel = temp_CSCS.base = temp_CS SHL 4RFLAGS.v = temp_RFLAGS // VIF,VIP,VM unchangedRIP = temp_RIPEXITIRET_PROTECTED:IF (RFLAGS.NT=1)// iret does a task-switch to a previous taskIF (LEGACY_MODE)TASK_SWITCH// using the ’back link’ field in the tssELSE// (LONG_MODE)EXCEPTION [#GP(0)] // task switches aren’t supported in long modePOP.v temp_RIPPOP.v temp_CSPOP.v temp_RFLAGSIF ((temp_RFLAGS.VM=1) && (CPL=0) && (LEGACY_MODE))IRET_FROM_PROTECTED_TO_VIRTUALtemp_CPL = temp_CS.rplIF ((64BIT_MODE) || (temp_CPL!=CPL)){POP.v temp_RSP// in 64-bit mode, iret always pops ss:rspPOP.v temp_SS}CS = READ_DESCRIPTOR (temp_CS, iret_chk)IF ((64BIT_MODE) && (temp_RIP is non-canonical)|| (!64BIT_MODE) && (temp_RIP > CS.limit)){EXCEPTION [#GP(0)]310 IRETx
24594 Rev. 3.10 February 2005 AMD64 Technology}CPL = temp_CPLIF ((started in 64-bit mode) || (changing CPL))// ss:rsp were popped, so load them into the registers{SS = READ_DESCRIPTOR (temp_SS, ss_chk)RSP.s = temp_RSP}IF (changing CPL){FOR (seg = ES, DS, FS, GS)IF ((seg.attr.dpl < CPL) && ((seg.attr.type = ’data’)|| (seg.attr.type = ’non-conforming-code’))){seg = NULL // can’t use lower dpl data segment at higher cpl}}RFLAGS.v = temp_RFLAGSRIP = temp_RIPEXIT// VIF,VIP,IOPL only changed if (old_CPL=0)// IF only changed if (old_CPL
- Page 290 and 291: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 292 and 293: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 294 and 295: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 296 and 297: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 298 and 299: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 300 and 301: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 302 and 303: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 304 and 305: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 306 and 307: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 308 and 309: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 310 and 311: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 312 and 313: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 314 and 315: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 316 and 317: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 318 and 319: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 320 and 321: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 322 and 323: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 324 and 325: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 326 and 327: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 328 and 329: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 330 and 331: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 332 and 333: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 334 and 335: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 336 and 337: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 338 and 339: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 342 and 343: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 344 and 345: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 346 and 347: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 348 and 349: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 350 and 351: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 352 and 353: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 354 and 355: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 356 and 357: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 358 and 359: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 360 and 361: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 362 and 363: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 364 and 365: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 366 and 367: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 368 and 369: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 370 and 371: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 372 and 373: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 374 and 375: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 376 and 377: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 378 and 379: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 380 and 381: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 382 and 383: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 384 and 385: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 386 and 387: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 388 and 389: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 Technology}CPL = temp_CPLIF ((started in 64-bit mode) || (changing CPL))// ss:rsp were popped, so load them into the registers{SS = READ_DESCRIPTOR (temp_SS, ss_chk)RSP.s = temp_RSP}IF (changing CPL){FOR (seg = ES, DS, FS, GS)IF ((seg.attr.dpl < CPL) && ((seg.attr.type = ’data’)|| (seg.attr.type = ’non-conforming-code’))){seg = NULL // can’t use lower dpl data segment at higher cpl}}RFLAGS.v = temp_RFLAGSRIP = temp_RIPEXIT// VIF,VIP,IOPL only changed if (old_CPL=0)// IF only changed if (old_CPL
Change language