Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005INVLPGInvalidate TLB EntryInvalidates the TLB entry that would be used for the 1-byte memory operand.This instruction invalidates the TLB entry, regardless of the G (Global) bit setting inthe associated PDE or PTE entry and regardless of the page size (4 Kbytes, 2 Mbytes,or 4 Mbytes). It may invalidate any number of additional TLB entries, in addition tothe targeted entry.INVLPG is a serializing instruction and a privileged instruction. The current privilegelevel must be 0 to execute this instruction.See “Page Translation and Protection” in Volume 2 for more information on pagetranslation.Mnemonic Opcode DescriptionINVLPG mem8 0F 01 /7 Invalidate the TLB entry for the page containing a specified memorylocation.Related InstructionsMOV CRn (CR3 and CR4)rFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X CPL was not 0.308 INVLPG
24594 Rev. 3.10 February 2005 AMD64 TechnologyIRETxIRETDIRETQReturn from InterruptReturns program control from an exception or interrupt handler to a program orprocedure previously interrupted by an exception, an external interrupt, or asoftware-generated interrupt. These instructions also perform a return from a nestedtask. All flags, CS, and rIP are restored to the values they had before the interrupt sothat execution may continue at the next instruction following the interrupt orexception. In 64-bit mode or if the CPL changes, SS and RSP are also restored.IRET, IRETD, and IRETQ are synonyms mapping to the same opcode. They areintended to provide semantically distinct forms for various opcode sizes. The IRETinstruction is used for 16-bit operand size; IRETD is used for 32-bit operand sizes;IRETQ is used for 64-bit operands. The latter form is only meaningful in 64-bit mode.IRET, IRETD, or IRETQ must be used to terminate the exception or interrupt handlerassociated with the exception, external interrupt, or software-generated interrupt.IRETx is a serializing instruction.For detailed descriptions of the steps performed by IRETx instructions, see thefollowing:• Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” inVolume 2.• Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in Volume 2.Mnemonic Opcode DescriptionIRET CF Return from interrupt (16-bit operand size).IRETD CF Return from interrupt (32-bit operand size).IRETQ CF Return from interrupt (64-bit operand size).ActionIRET_START:IF (REAL_MODE)IRET_REALELSIF (PROTECTED_MODE)IRETx 309
- Page 288 and 289: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 290 and 291: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 292 and 293: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 294 and 295: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 296 and 297: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 298 and 299: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 300 and 301: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 302 and 303: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 304 and 305: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 306 and 307: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 308 and 309: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 310 and 311: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 312 and 313: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 314 and 315: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 316 and 317: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 318 and 319: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 320 and 321: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 322 and 323: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 324 and 325: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 326 and 327: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 328 and 329: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 330 and 331: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 332 and 333: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 334 and 335: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 336 and 337: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 340 and 341: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 342 and 343: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 344 and 345: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 346 and 347: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 348 and 349: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 350 and 351: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 352 and 353: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 354 and 355: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 356 and 357: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 358 and 359: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 360 and 361: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 362 and 363: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 364 and 365: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 366 and 367: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 368 and 369: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 370 and 371: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 372 and 373: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 374 and 375: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 376 and 377: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 378 and 379: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 380 and 381: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 382 and 383: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 384 and 385: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 386 and 387: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 TechnologyIRETxIRETDIRETQReturn from InterruptReturns program control from an exception or interrupt h<strong>and</strong>ler to a program orprocedure previously interrupted by an exception, an external interrupt, or asoftware-generated interrupt. These instructions also perform a return from a nestedtask. All flags, CS, <strong>and</strong> rIP are restored to the values they had before the interrupt sothat execution may continue at the next instruction following the interrupt orexception. In 64-bit mode or if the CPL changes, SS <strong>and</strong> RSP are also restored.IRET, IRETD, <strong>and</strong> IRETQ are synonyms mapping to the same opcode. They areintended to provide semantically distinct forms for various opcode sizes. The IRETinstruction is used for 16-bit oper<strong>and</strong> size; IRETD is used for 32-bit oper<strong>and</strong> sizes;IRETQ is used for 64-bit oper<strong>and</strong>s. The latter form is only meaningful in 64-bit mode.IRET, IRETD, or IRETQ must be used to terminate the exception or interrupt h<strong>and</strong>lerassociated with the exception, external interrupt, or software-generated interrupt.IRETx is a serializing instruction.For detailed descriptions of the steps performed by IRETx instructions, see thefollowing:• Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” in<strong>Volume</strong> 2.• Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in <strong>Volume</strong> 2.Mnemonic Opcode DescriptionIRET CF Return from interrupt (16-bit oper<strong>and</strong> size).IRETD CF Return from interrupt (32-bit oper<strong>and</strong> size).IRETQ CF Return from interrupt (64-bit oper<strong>and</strong> size).ActionIRET_START:IF (REAL_MODE)IRET_REALELSIF (PROTECTED_MODE)IRETx 309
Change language