Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005INVLPGInvalidate TLB EntryInvalidates the TLB entry that would be used for the 1-byte memory operand.This instruction invalidates the TLB entry, regardless of the G (Global) bit setting inthe associated PDE or PTE entry and regardless of the page size (4 Kbytes, 2 Mbytes,or 4 Mbytes). It may invalidate any number of additional TLB entries, in addition tothe targeted entry.INVLPG is a serializing instruction and a privileged instruction. The current privilegelevel must be 0 to execute this instruction.See “Page Translation and Protection” in Volume 2 for more information on pagetranslation.Mnemonic Opcode DescriptionINVLPG mem8 0F 01 /7 Invalidate the TLB entry for the page containing a specified memorylocation.Related InstructionsMOV CRn (CR3 and CR4)rFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X CPL was not 0.308 INVLPG
24594 Rev. 3.10 February 2005 AMD64 TechnologyIRETxIRETDIRETQReturn from InterruptReturns program control from an exception or interrupt handler to a program orprocedure previously interrupted by an exception, an external interrupt, or asoftware-generated interrupt. These instructions also perform a return from a nestedtask. All flags, CS, and rIP are restored to the values they had before the interrupt sothat execution may continue at the next instruction following the interrupt orexception. In 64-bit mode or if the CPL changes, SS and RSP are also restored.IRET, IRETD, and IRETQ are synonyms mapping to the same opcode. They areintended to provide semantically distinct forms for various opcode sizes. The IRETinstruction is used for 16-bit operand size; IRETD is used for 32-bit operand sizes;IRETQ is used for 64-bit operands. The latter form is only meaningful in 64-bit mode.IRET, IRETD, or IRETQ must be used to terminate the exception or interrupt handlerassociated with the exception, external interrupt, or software-generated interrupt.IRETx is a serializing instruction.For detailed descriptions of the steps performed by IRETx instructions, see thefollowing:• Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” inVolume 2.• Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in Volume 2.Mnemonic Opcode DescriptionIRET CF Return from interrupt (16-bit operand size).IRETD CF Return from interrupt (32-bit operand size).IRETQ CF Return from interrupt (64-bit operand size).ActionIRET_START:IF (REAL_MODE)IRET_REALELSIF (PROTECTED_MODE)IRETx 309
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AMD64 Technology 24594 Rev. 3.10 February 2005INVLPGInvalidate TLB EntryInvalidates the TLB entry that would be used for the 1-byte memory oper<strong>and</strong>.This instruction invalidates the TLB entry, regardless of the G (Global) bit setting inthe associated PDE or PTE entry <strong>and</strong> regardless of the page size (4 Kbytes, 2 Mbytes,or 4 Mbytes). It may invalidate any number of additional TLB entries, in addition tothe targeted entry.INVLPG is a serializing instruction <strong>and</strong> a privileged instruction. The current privilegelevel must be 0 to execute this instruction.See “Page Translation <strong>and</strong> Protection” in <strong>Volume</strong> 2 for more information on pagetranslation.Mnemonic Opcode DescriptionINVLPG mem8 0F 01 /7 Invalidate the TLB entry for the page containing a specified memorylocation.Related <strong>Instructions</strong>MOV CRn (CR3 <strong>and</strong> CR4)rFLAGS AffectedNoneExceptionsException<strong>General</strong> protection,#GPRealVirtual8086 Protected Cause of ExceptionX X CPL was not 0.308 INVLPG