Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Stack, #SS(selector)ExceptionRealVirtual8086 Protected Cause of ExceptionXXAfter a stack switch, a memory address exceeded the stack segmentlimit or was non-canonical and a stack switch occurred.XXAs part of a stack switch, the SS register was loaded with a non-nullsegment selector and the segment was marked not present.General protection,#GPXXXA memory address exceeded the data segment limit or was noncanonical.XXXThe target offset exceeded the code segment limit or was noncanonical.General protection,#GP(selector)XXXXXThe interrupt vector was beyond the limit of IDT.The descriptor in the IDT was not an interrupt, trap, or task gate inlegacy mode or not a 64-bit interrupt or trap gate in long mode.XXThe DPL of the interrupt, trap, or task gate descriptor was less thanthe CPL.XXThe segment selector specified by the interrupt or trap gate had its TIbit set, but the LDT selector was a null selector.XXThe segment descriptor specified by the interrupt or trap gateexceeded the descriptor table limit or was a null selector.XXThe segment descriptor specified by the interrupt or trap gate wasnot a code segment in legacy mode, or not a 64-bit code segment inlong mode.XThe DPL of the segment specified by the interrupt or trap gate wasgreater than the CPL.XThe DPL of the segment specified by the interrupt or trap gatepointed was not 0 or it was a conforming segment.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.306 INT 3
24594 Rev. 3.10 February 2005 AMD64 TechnologyINVDInvalidate CachesInvalidates internal caches (data cache, instruction cache, and on-chip L2 cache) andtriggers a bus cycle that causes external caches to invalidate themselves as well.No data is written back to main memory from invalidating internal caches. Afterinvalidating internal caches, the processor proceeds immediately with the executionof the next instruction without waiting for external hardware to invalidate its caches.This is a privileged instruction. The current privilege level (CPL) of a procedureinvalidating the processor’s internal caches must be 0.To insure that data is written back to memory prior to invalidating caches, use theWBINVD instruction.This instruction does not invalidate TLB caches.INVD is a serializing instruction.Mnemonic Opcode DescriptionINVD 0F 08 Flush internal caches and trigger external cache flushes.Related InstructionsWBINVD, CLFLUSHrFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X CPL was not 0.INVD 307
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AMD64 Technology 24594 Rev. 3.10 February 2005Stack, #SS(selector)ExceptionRealVirtual8086 Protected Cause of ExceptionXXAfter a stack switch, a memory address exceeded the stack segmentlimit or was non-canonical <strong>and</strong> a stack switch occurred.XXAs part of a stack switch, the SS register was loaded with a non-nullsegment selector <strong>and</strong> the segment was marked not present.<strong>General</strong> protection,#GPXXXA memory address exceeded the data segment limit or was noncanonical.XXXThe target offset exceeded the code segment limit or was noncanonical.<strong>General</strong> protection,#GP(selector)XXXXXThe interrupt vector was beyond the limit of IDT.The descriptor in the IDT was not an interrupt, trap, or task gate inlegacy mode or not a 64-bit interrupt or trap gate in long mode.XXThe DPL of the interrupt, trap, or task gate descriptor was less thanthe CPL.XXThe segment selector specified by the interrupt or trap gate had its TIbit set, but the LDT selector was a null selector.XXThe segment descriptor specified by the interrupt or trap gateexceeded the descriptor table limit or was a null selector.XXThe segment descriptor specified by the interrupt or trap gate wasnot a code segment in legacy mode, or not a 64-bit code segment inlong mode.XThe DPL of the segment specified by the interrupt or trap gate wasgreater than the CPL.XThe DPL of the segment specified by the interrupt or trap gatepointed was not 0 or it was a conforming segment.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.306 INT 3
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