Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologyrFLAGS AffectedIf a task switch occurs, all flags are modified; otherwise, setting are as follows:ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM 0 0 M M 021 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flags are blank. Undefinedflags are U.VirtualException Real 8086 Protected Cause of ExceptionBreakpoint, #BP X X X INT 3 instruction was executed.Invalid TSS, #TS(selector)XXAs part of a stack switch, the target stack segment selector or rSP inthe TSS was that was beyond the TSS limit.XXXXXXXXXXAs part of a stack switch, the target stack segment selector in the TSSwas beyond the limit of the GDT or LDT descriptor table.As part of a stack switch, the target stack segment selector in the TSSwas a null selector.As part of a stack switch, the target stack segment selector’s TI bit wasset, but the LDT selector was a null selector.As part of a stack switch, the target stack segment selector in the TSScontained a RPL that was not equal to its DPL.As part of a stack switch, the target stack segment selector in the TSScontained a DPL that was not equal to the CPL of the code segmentselector.Segment not present,#NP (selector)XXAs part of a stack switch, the target stack segment selector in the TSSwas not a writable segment.X X The accessed code segment, interrupt gate, trap gate, task gate, orTSS was not present.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.INT 3 305