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AMD64 Technology 24594 Rev. 3.10 February 2005CLIClear Interrupt FlagClears the interrupt flag (IF) in the rFLAGS register to zero, thereby masking externalinterrupts received on the INTR input. Interrupts received on the non-maskableinterrupt (NMI) input are not affected by this instruction.In real mode, this instruction clears IF to 0.In protected mode and virtual-8086-mode, this instruction is IOPL-sensitive. If theCPL is less than or equal to the rFLAGS.IOPL field, the instruction clears IF to 0.In protected mode, if IOPL < 3, CPL = 3, and protected mode virtual interrupts areenabled (CR4.PVI = 1), then the instruction instead clears rFLAGS.VIF to 0. If none ofthese conditions apply, the processor raises a general-purpose exception (#GP). Formore information, see “Protected Mode Virtual Interrupts” in Volume 2.In virtual-8086 mode, if IOPL < 3 and the virtual-8086-mode extensions are enabled(CR4.VME = 1), the CLI instruction clears the virtual interrupt flag (rFLAGS.VIF) to0 instead.See “Virtual-8086 Mode Extensions” in Volume 2 for more information about IOPLsensitiveinstructions.Mnemonic Opcode DescriptionCLI FA Clear the interrupt flag (IF) to zero.ActionIF (CPL
24594 Rev. 3.10 February 2005 AMD64 TechnologyrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFMM21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionXThe CPL was greater than the IOPL and virtual mode extensions arenot enabled (CR4.VME = 0).XThe CPL was greater than the IOPL and either the CPL was not 3 orprotected mode virtual interrupts were not enabled (CR4.PVI = 0).CLI 301
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