Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005CLIClear Interrupt FlagClears the interrupt flag (IF) in the rFLAGS register to zero, thereby masking externalinterrupts received on the INTR input. Interrupts received on the non-maskableinterrupt (NMI) input are not affected by this instruction.In real mode, this instruction clears IF to 0.In protected mode and virtual-8086-mode, this instruction is IOPL-sensitive. If theCPL is less than or equal to the rFLAGS.IOPL field, the instruction clears IF to 0.In protected mode, if IOPL < 3, CPL = 3, and protected mode virtual interrupts areenabled (CR4.PVI = 1), then the instruction instead clears rFLAGS.VIF to 0. If none ofthese conditions apply, the processor raises a general-purpose exception (#GP). Formore information, see “Protected Mode Virtual Interrupts” in Volume 2.In virtual-8086 mode, if IOPL < 3 and the virtual-8086-mode extensions are enabled(CR4.VME = 1), the CLI instruction clears the virtual interrupt flag (rFLAGS.VIF) to0 instead.See “Virtual-8086 Mode Extensions” in Volume 2 for more information about IOPLsensitiveinstructions.Mnemonic Opcode DescriptionCLI FA Clear the interrupt flag (IF) to zero.ActionIF (CPL
24594 Rev. 3.10 February 2005 AMD64 TechnologyrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFMM21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionXThe CPL was greater than the IOPL and virtual mode extensions arenot enabled (CR4.VME = 0).XThe CPL was greater than the IOPL and either the CPL was not 3 orprotected mode virtual interrupts were not enabled (CR4.PVI = 0).CLI 301
- Page 280 and 281: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 282 and 283: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 284 and 285: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 286 and 287: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 288 and 289: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 290 and 291: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 292 and 293: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 294 and 295: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 296 and 297: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 298 and 299: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 300 and 301: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 302 and 303: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 304 and 305: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 306 and 307: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 308 and 309: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 310 and 311: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 312 and 313: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 314 and 315: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 316 and 317: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 318 and 319: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 320 and 321: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 322 and 323: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 324 and 325: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 326 and 327: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 328 and 329: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 332 and 333: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 334 and 335: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 336 and 337: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 338 and 339: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 340 and 341: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 342 and 343: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 344 and 345: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 346 and 347: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 348 and 349: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 350 and 351: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 352 and 353: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 354 and 355: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 356 and 357: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 358 and 359: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 360 and 361: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 362 and 363: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 364 and 365: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 366 and 367: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 368 and 369: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 370 and 371: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 372 and 373: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 374 and 375: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 376 and 377: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 378 and 379: AMD64 Technology 24594 Rev. 3.10 Fe
AMD64 Technology 24594 Rev. 3.10 February 2005CLIClear Interrupt FlagClears the interrupt flag (IF) in the rFLAGS register to zero, thereby masking externalinterrupts received on the INTR input. Interrupts received on the non-maskableinterrupt (NMI) input are not affected by this instruction.In real mode, this instruction clears IF to 0.In protected mode <strong>and</strong> virtual-8086-mode, this instruction is IOPL-sensitive. If theCPL is less than or equal to the rFLAGS.IOPL field, the instruction clears IF to 0.In protected mode, if IOPL < 3, CPL = 3, <strong>and</strong> protected mode virtual interrupts areenabled (CR4.PVI = 1), then the instruction instead clears rFLAGS.VIF to 0. If none ofthese conditions apply, the processor raises a general-purpose exception (#GP). Formore information, see “Protected Mode Virtual Interrupts” in <strong>Volume</strong> 2.In virtual-8086 mode, if IOPL < 3 <strong>and</strong> the virtual-8086-mode extensions are enabled(CR4.VME = 1), the CLI instruction clears the virtual interrupt flag (rFLAGS.VIF) to0 instead.See “Virtual-8086 Mode Extensions” in <strong>Volume</strong> 2 for more information about IOPLsensitiveinstructions.Mnemonic Opcode DescriptionCLI FA Clear the interrupt flag (IF) to zero.ActionIF (CPL