Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionXOR reg/mem32, imm32XOR reg/mem64, imm32XOR reg/mem16, imm8XOR reg/mem32, imm8XOR reg/mem64, imm881 /6 id81 /6 id83 /6 ib83 /6 ib83 /6 ibXOR the contents of a 32-bit destination register or memoryoperand with a 32-bit immediate value and store the result in thedestination.XOR the contents of a 64-bit destination register or memoryoperand with a sign-extended 32-bit immediate value and storethe result in the destination.XOR the contents of a 16-bit destination register or memoryoperand with a sign-extended 8-bit immediate value and storethe result in the destination.XOR the contents of a 32-bit destination register or memoryoperand with a sign-extended 8-bit immediate value and storethe result in the destination.XOR the contents of a 64-bit destination register or memoryoperand with a sign-extended 8-bit immediate value and storethe result in the destination.XOR reg/mem8, reg8 30 /rXOR reg/mem16, reg16 31 /rXOR reg/mem32, reg32 31 /rXOR reg/mem64, reg64 31 /rXOR reg8, reg/mem8 32 /rXOR reg16, reg/mem16 33 /rXOR reg32, reg/mem32 33 /rXOR reg64, reg/mem64 33 /rXOR the contents of an 8-bit destination register or memoryoperand with the contents of an 8-bit register and store the resultin the destination.XOR the contents of a 16-bit destination register or memoryoperand with the contents of a 16-bit register and store the resultin the destination.XOR the contents of a 32-bit destination register or memoryoperand with the contents of a 32-bit register and store the resultin the destination.XOR the contents of a 64-bit destination register or memoryoperand with the contents of a 64-bit register and store the resultin the destination.XOR the contents of an 8-bit destination register with thecontents of an 8-bit register or memory operand and store theresults in the destination.XOR the contents of a 16-bit destination register with the contentsof a 16-bit register or memory operand and store the results inthe destination.XOR the contents of a 32-bit destination register with thecontents of a 32-bit register or memory operand and store theresults in the destination.XOR the contents of a 64-bit destination register with thecontents of a 64-bit register or memory operand and store theresults in the destination.294 XOR
24594 Rev. 3.10 February 2005 AMD64 TechnologyRelated InstructionsOR, AND, NOT, NEGrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptions0 M M U M 021 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.XOR 295
- Page 274 and 275: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 276 and 277: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 278 and 279: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 280 and 281: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 282 and 283: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 284 and 285: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 286 and 287: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 288 and 289: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 290 and 291: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 292 and 293: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 294 and 295: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 296 and 297: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 298 and 299: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 300 and 301: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 302 and 303: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 304 and 305: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 306 and 307: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 308 and 309: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 310 and 311: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 312 and 313: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 314 and 315: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 316 and 317: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 318 and 319: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 320 and 321: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 322 and 323: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 326 and 327: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 328 and 329: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 330 and 331: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 332 and 333: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 334 and 335: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 336 and 337: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 338 and 339: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 340 and 341: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 342 and 343: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 344 and 345: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 346 and 347: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 348 and 349: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 350 and 351: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 352 and 353: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 354 and 355: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 356 and 357: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 358 and 359: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 360 and 361: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 362 and 363: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 364 and 365: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 366 and 367: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 368 and 369: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 370 and 371: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 372 and 373: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 TechnologyRelated <strong>Instructions</strong>OR, AND, NOT, NEGrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptions0 M M U M 021 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination oper<strong>and</strong> was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.XOR 295
Change language