Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.288 XADD
24594 Rev. 3.10 February 2005 AMD64 TechnologyXCHGExchangeExchanges the contents of the two operands. The operands can be two generalpurposeregisters or a register and a memory location. If either operand referencesmemory, the processor locks automatically, whether or not the LOCK prefix is usedand independently of the value of IOPL. For details about the LOCK prefix, see “LockPrefix” on page 10.The x86 architecture commonly uses the XCHG EAX, EAX instruction (opcode 90h) asa one-byte NOP. In 64-bit mode, the processor treats opcode 90h as a true NOP only ifit would exchange rAX with itself. Without this special handling, the instructionwould zero-extend the upper 32 bits of RAX, and thus it would not be a true nooperation.Opcode 90h can still be used to exchange rAX and r8 if the appropriateREX prefix is used.This special handling does not apply to the two-byte ModRM form of the XCHGinstruction.Mnemonic Opcode DescriptionXCHG AX, reg1690 +rwXCHG reg16, AX90 +rwXCHG EAX, reg3290 +rdXCHG reg32, EAX90 +rdXCHG RAX, reg6490 +rqXCHG reg64, RAX90 +rqXCHG reg/mem8, reg8 86 /rXCHG reg8, reg/mem8 86 /rXCHG reg/mem16, reg16 87 /rExchange the contents of the AX register with the contents of a16-bit register.Exchange the contents of a 16-bit register with the contents of theAX register.Exchange the contents of the EAX register with the contents of a32-bit register.Exchange the contents of a 32-bit register with the contents of theEAX register.Exchange the contents of the RAX register with the contents of a64-bit register.Exchange the contents of a 64-bit register with the contents ofthe RAX register.Exchange the contents of an 8-bit register with the contents of an8-bit register or memory operand.Exchange the contents of an 8-bit register or memory operandwith the contents of an 8-bit register.Exchange the contents of a 16-bit register with the contents of a16-bit register or memory operand.XCHG 289
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AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination oper<strong>and</strong> was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.288 XADD
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