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AMD64 Technology 24594 Rev. 3.10 February 2005SHRShift RightShifts the bits of a register or memory location (first operand) to the right through theCF bit by the number of bit positions in an unsigned immediate value or the CLregister (second operand). The instruction discards bits shifted out of the CF flag. Atthe end of the shift operation, the CF flag contains the last bit shifted out of the firstoperand.For each bit shift, the instruction clears the most-significant bit to 0.The effect of this instruction is unsigned division by powers of two.The processor masks the upper three bits of the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, theprocessor masks the upper two bits of the count, providing a count in the range of 0 to63.For 1-bit shifts, the instruction sets the OF flag to the most-significant bit of theoriginal value. If the count is greater than 1, the OF flag is undefined.If the shift count is 0, no flags are modified.Mnemonic Opcode DescriptionSHR reg/mem8, 1 D0 /5 Shift an 8-bit register or memory operand right 1 bit.SHR reg/mem8, CL D2 /5SHR reg/mem8, imm8C0 /5 ibShift an 8-bit register or memory operand right the number ofbits specified in the CL register.Shift an 8-bit register or memory operand right the number ofbits specified by an 8-bit immediate value.SHR reg/mem16, 1 D1 /5 Shift a 16-bit register or memory operand right 1 bit.SHR reg/mem16, CL D3 /5SHR reg/mem16, imm8C1 /5 ibShift a 16-bit register or memory operand right the number ofbits specified in the CL register.Shift a 16-bit register or memory operand right the number ofbits specified by an 8-bit immediate value.SHR reg/mem32, 1 D1 /5 Shift a 32-bit register or memory operand right 1 bit.SHR reg/mem32, CL D3 /5SHR reg/mem32, imm8C1 /5 ibShift a 32-bit register or memory operand right the number ofbits specified in the CL register.Shift a 32-bit register or memory operand right the number ofbits specified by an 8-bit immediate value.274 SHR
24594 Rev. 3.10 February 2005 AMD64 TechnologySHR reg/mem64, 1 D1 /5 Shift a 64-bit register or memory operand right 1 bit.SHR reg/mem64, CL D3 /5Shift a 64-bit register or memory operand right the number ofbits specified in the CL register.SHR reg/mem64, imm8Related InstructionsC1 /5 ibShift a 64-bit register or memory operand right the number ofbits specified by an 8-bit immediate value.SHL, SAL, SAR, SHLD, SHRDrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M U M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.SHR 275
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