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AMD64 Technology 24594 Rev. 3.10 February 2005SHLDShift Left DoubleShifts the bits of a register or memory location (first operand) to the left by thenumber of bit positions in an unsigned immediate value or the CL register (thirdoperand), and shifts in a bit pattern (second operand) from the right. At the end of theshift operation, the CF flag contains the last bit shifted out of the first operand.The processor masks the upper three bits of the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, theprocessor masks the upper two bits of the count, providing a count in the range of 0 to63. If the masked count is greater than the operand size, the result in the destinationregister is undefined.If the shift count is 0, no flags are modified.If the count is 1 and the sign of the operand being shifted changes, the instruction setsthe OF flag to 1. If the count is greater than 1, OF is undefined.Mnemonic Opcode DescriptionSHLD reg/mem16, reg16, imm80F A4 /r ibShift bits of a 16-bit destination register or memory operand tothe left the number of bits specified in an 8-bit immediate value,while shifting in bits from the second operand.SHLD reg/mem16, reg16, CL 0F A5 /rShift bits of a 16-bit destination register or memory operand tothe left the number of bits specified in the CL register, whileshifting in bits from the second operand.SHLD reg/mem32, reg32, imm80F A4 /r ibShift bits of a 32-bit destination register or memory operand tothe left the number of bits specified in an 8-bit immediate value,while shifting in bits from the second operand.SHLD reg/mem32, reg32, CL 0F A5 /rShift bits of a 32-bit destination register or memory operand tothe left the number of bits specified in the CL register, whileshifting in bits from the second operand.SHLD reg/mem64, reg64, imm80F A4 /r ibShift bits of a 64-bit destination register or memory operand tothe left the number of bits specified in an 8-bit immediate value,while shifting in bits from the second operand.SHLD reg/mem64, reg64, CL 0F A5 /rShift bits of a 64-bit destination register or memory operand tothe left the number of bits specified in the CL register, whileshifting in bits from the second operand.272 SHLD
24594 Rev. 3.10 February 2005 AMD64 TechnologyRelated InstructionsSHRD, SAL, SAR, SHR, SHLrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M U M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.SHLD 273
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