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AMD64 Technology 24594 Rev. 3.10 February 2005SFENCEStore FenceActs as a barrier to force strong memory ordering (serialization) between storeinstructions preceding the SFENCE and store instructions that follow the SFENCE. Aweakly-ordered memory system allows hardware to reorder reads and writes betweenthe processor and memory. The SFENCE instruction guarantees that the systemcompletes all previous stores before executing subsequent stores.The SFENCE instruction is weakly-ordered with respect to load instructions, data andinstruction prefetches, and the LFENCE instruction. Speculative loads initiated bythe processor, or specified explicitly using cache-prefetch instructions, can bereordered around an SFENCE.In addition to store instructions, SFENCE is strongly ordered with respect to otherSFENCE instructions, MFENCE instructions, and serializing instructions.Support for the SFENCE instruction is indicated when the SSE bit (bit 25) is set to 1 inEDX after executing CPUID standard function 1.Mnemonic Opcode DescriptionSFENCE 0F AE F8 Force strong ordering of (serialized) store operations.Related InstructionsLFENCE, MFENCErFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid Opcode, #UD X X X The SSE instructions are not supported, as indicated by EDX bit 25 ofCPUID standard function 1; and the AMD extensions to MMX are notsupported, as indicated by EDX bit 22 of CPUID extended function8000_0001h.270 SFENCE
24594 Rev. 3.10 February 2005 AMD64 TechnologySHLShift LeftThis instruction is synonymous with the SAL instruction. For information, see “SALSHL” on page 256.SHL 271
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