Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M U M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.258 SAL, SHL
24594 Rev. 3.10 February 2005 AMD64 TechnologySARShift Arithmetic RightShifts the bits of a register or memory location (first operand) to the right through theCF bit by the number of bit positions in an unsigned immediate value or the CLregister (second operand). The instruction discards bits shifted out of the CF flag. Atthe end of the shift operation, the CF flag contains the last bit shifted out of the firstoperand.The SAR instruction does not change the sign bit of the target operand. For each bitshift, it copies the sign bit to the next bit, preserving the sign of the result.The processor masks the upper three bits of the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, theprocessor masks the upper two bits of the count, providing a count in the range of 0 to63.For 1-bit shifts, the instruction clears the OF flag to 0. When the shift count is greaterthan 1, the OF flag is undefined.If the shift count is 0, no flags are modified.Although the SAR instruction effectively divides the operand by a power of 2, thebehavior is different from the IDIV instruction. For example, shifting –11(FFFFFFF5h) by two bits to the right (that is, divide –11 by 4), gives a result ofFFFFFFFDh, or –3, whereas the IDIV instruction for dividing –11 by 4 gives a result of–2. This is because the IDIV instruction rounds off the quotient to zero, whereas theSAR instruction rounds off the remainder to zero for positive dividends and tonegative infinity for negative dividends. So, for positive operands, SAR behaves likethe corresponding IDIV instruction. For negative operands, it gives the same result ifand only if all the shifted-out bits are zeroes; otherwise, the result is smaller by 1.Mnemonic Opcode DescriptionSAR reg/mem8, 1 D0 /7 Shift a signed 8-bit register or memory operand right 1 bit.SAR reg/mem8, CL D2 /7SAR reg/mem8, imm8C0 /7 ibShift a signed 8-bit register or memory operand right the numberof bits specified in the CL register.Shift a signed 8-bit register or memory operand right the numberof bits specified by an 8-bit immediate value.SAR reg/mem16, 1 D1 /7 Shift a signed 16-bit register or memory operand right 1 bit.SAR 259
- Page 238 and 239: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 240 and 241: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 242 and 243: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 244 and 245: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 246 and 247: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 248 and 249: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 250 and 251: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 252 and 253: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 254 and 255: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 256 and 257: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 258 and 259: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 260 and 261: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 262 and 263: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 264 and 265: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 266 and 267: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 268 and 269: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 270 and 271: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 272 and 273: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 274 and 275: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 276 and 277: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 278 and 279: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 280 and 281: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 282 and 283: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 284 and 285: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 286 and 287: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 290 and 291: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 292 and 293: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 294 and 295: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 296 and 297: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 298 and 299: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 300 and 301: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 302 and 303: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 304 and 305: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 306 and 307: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 308 and 309: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 310 and 311: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 312 and 313: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 314 and 315: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 316 and 317: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 318 and 319: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 320 and 321: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 322 and 323: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 324 and 325: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 326 and 327: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 328 and 329: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 330 and 331: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 332 and 333: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 334 and 335: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 336 and 337: AMD64 Technology 24594 Rev. 3.10 Fe
AMD64 Technology 24594 Rev. 3.10 February 2005rFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M U M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination oper<strong>and</strong> was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.258 SAL, SHL
Change language