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AMD64 Technology 24594 Rev. 3.10 February 2005SALSHLShift LeftShifts the bits of a register or memory location (first operand) to the left through theCF bit by the number of bit positions in an unsigned immediate value or the CLregister (second operand). The instruction discards bits shifted out of the CF flag. Foreach bit shift, the SAL instruction clears the least-significant bit to 0. At the end of theshift operation, the CF flag contains the last bit shifted out of the first operand.The processor masks the upper three bits of the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, theprocessor masks the upper two bits of the count, providing a count in the range of 0 to63.The effect of this instruction is multiplication by powers of two.For 1-bit shifts, the instruction sets the OF flag to the exclusive OR of the CF bit (afterthe shift) and the most significant bit of the result. When the shift count is greaterthan 1, the OF flag is undefined.If the shift count is 0, no flags are modified.SHL is an alias to the SAL instruction.Mnemonic Opcode DescriptionSAL reg/mem8, 1 D0 /4 Shift an 8-bit register or memory location left 1 bit.SAL reg/mem8, CL D2 /4SAL reg/mem8, imm8C0 /4 ibShift an 8-bit register or memory location left the number of bitsspecified in the CL register.Shift an 8-bit register or memory location left the number of bitsspecified by an 8-bit immediate value.SAL reg/mem16, 1 D1 /4 Shift a 16-bit register or memory location left 1 bit.SAL reg/mem16, CL D3 /4SAL reg/mem16, imm8C1 /4 ibShift a 16-bit register or memory location left the number of bitsspecified in the CL register.Shift a 16-bit register or memory location left the number of bitsspecified by an 8-bit immediate value.SAL reg/mem32, 1 D1 /4 Shift a 32-bit register or memory location left 1 bit.SAL reg/mem32, CL D3 /4Shift a 32-bit register or memory location left the number of bitsspecified in the CL register.256 SAL, SHL
24594 Rev. 3.10 February 2005 AMD64 TechnologyMnemonic Opcode DescriptionSAL reg/mem32, imm8Related InstructionsSAR, SHR, SHLD, SHRDC1 /4 ibShift a 32-bit register or memory location left the number of bitsspecified by an 8-bit immediate value.SAL reg/mem64, 1 D1 /4 Shift a 64-bit register or memory location left 1 bit.SAL reg/mem64, CL D3 /4SAL reg/mem64, imm8C1 /4 ibShift a 64-bit register or memory location left the number of bitsspecified in the CL register.Shift a 64-bit register or memory location left the number of bitsspecified by an 8-bit immediate value.SHL reg/mem8, 1 D0 /4 Shift an 8-bit register or memory location by 1 bit.SHL reg/mem8, CL D2 /4SHL reg/mem8, imm8C0 /4 ibShift an 8-bit register or memory location left the number of bitsspecified in the CL register.Shift an 8-bit register or memory location left the number of bitsspecified by an 8-bit immediate value.SHL reg/mem16, 1 D1 /4 Shift a 16-bit register or memory location left 1 bit.SHL reg/mem16, CL D3 /4SHL reg/mem16, imm8C1 /4 ibShift a 16-bit register or memory location left the number of bitsspecified in the CL register.Shift a 16-bit register or memory location left the number of bitsspecified by an 8-bit immediate value.SHL reg/mem32, 1 D1 /4 Shift a 32-bit register or memory location left 1 bit.SHL reg/mem32, CL D3 /4SHL reg/mem32, imm8C1 /4 ibShift a 32-bit register or memory location left the number of bitsspecified in the CL register.Shift a 32-bit register or memory location left the number of bitsspecified by an 8-bit immediate value.SHL reg/mem64, 1 D1 /4 Shift a 64-bit register or memory location left 1 bit.SHL reg/mem64, CL D3 /4SHL reg/mem64, imm8C1 /4 ibShift a 64-bit register or memory location left the number of bitsspecified in the CL register.Shift a 64-bit register or memory location left the number of bitsspecified by an 8-bit immediate value.SAL, SHL 257
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