Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionROR reg/mem64, CL D3 /1Rotate a 64-bit register or memory operand right the number ofbits specified in the CL register.ROR reg/mem64, imm8Related InstructionsRCL, RCR, ROLrFLAGS AffectedC1 /1 ibRotate a 64-bit register or memory operand right the number ofbits specified by an 8-bit immediate value.ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFMM21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.254 ROR
24594 Rev. 3.10 February 2005 AMD64 TechnologySAHFStore AH into FlagsLoads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from thecorresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively). Theinstruction ignores bits 1, 3, and 5 of register AH; it sets those bits in the EFLAGSregister to 1, 0, and 0, respectively.The SAHF instruction can only be executed in 64-bit mode if supported by theprocessor implementation. Check the status of ECX bit 0 returned by CPUIDextended function 8000_0001h to verify that the processor supports SAHF in 64-bitmode.Mnemonic Opcode DescriptionSAHFRelated InstructionsLAHFrFLAGS Affected9ELoads the sign flag, the zero flag, the auxiliary flag, the parity flag,and the carry flag from the AH register into the lower 8 bits of theEFLAGS register.ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X This instruction is not supported in 64-bit mode, as indicated by ECXbit 0 returned by CPUID standard function 8000_0001h.SAHF 255
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24594 Rev. 3.10 February 2005 AMD64 TechnologySAHFStore AH into FlagsLoads the SF, ZF, AF, PF, <strong>and</strong> CF flags of the EFLAGS register with values from thecorresponding bits in the AH register (bits 7, 6, 4, 2, <strong>and</strong> 0, respectively). Theinstruction ignores bits 1, 3, <strong>and</strong> 5 of register AH; it sets those bits in the EFLAGSregister to 1, 0, <strong>and</strong> 0, respectively.The SAHF instruction can only be executed in 64-bit mode if supported by theprocessor implementation. Check the status of ECX bit 0 returned by CPUIDextended function 8000_0001h to verify that the processor supports SAHF in 64-bitmode.Mnemonic Opcode DescriptionSAHFRelated <strong>Instructions</strong>LAHFrFLAGS Affected9ELoads the sign flag, the zero flag, the auxiliary flag, the parity flag,<strong>and</strong> the carry flag from the AH register into the lower 8 bits of theEFLAGS register.ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X This instruction is not supported in 64-bit mode, as indicated by ECXbit 0 returned by CPUID st<strong>and</strong>ard function 8000_0001h.SAHF 255
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