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AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionROL reg/mem64, CL D3 /0Rotate a 64-bit register or memory operand left the number ofbits specified in the CL register.ROL reg/mem64, imm8Related InstructionsRCL, RCR, RORrFLAGS AffectedC1 /0 ibRotate a 64-bit register or memory operand left the number ofbits specified by an 8-bit immediate value.ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFMM21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.252 ROL
24594 Rev. 3.10 February 2005 AMD64 TechnologyRORRotate RightRotates the bits of a register or memory location (first operand) to the right (towardthe less significant bit positions) by the number of bit positions in an unsignedimmediate value or the CL register (second operand). The bits rotated out right arerotated back in at the left end (the most significant bit) of the first operand location.The processor masks the upper three bits of the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, theprocessor masks the upper two bits of the count, providing a count in the range of 0 to63.After completing the rotation, the instruction sets the CF flag to the last bit rotatedout (the most significant bit of the result). For 1-bit rotates, the instruction sets the OFflag to the exclusive OR of the two most significant bits of the result. When the rotatecount is greater than 1, the OF flag is undefined. When the rotate count is 0, no flagsare affected.Mnemonic Opcode DescriptionROR reg/mem8, 1 D0 /1 Rotate an 8-bit register or memory location right 1 bit.ROR reg/mem8, CL D2 /1ROR reg/mem8, imm8C0 /1 ibRotate an 8-bit register or memory location right the number ofbits specified in the CL register.Rotate an 8-bit register or memory location right the number ofbits specified by an 8-bit immediate value.ROR reg/mem16, 1 D1 /1 Rotate a 16-bit register or memory location right 1 bit.ROR reg/mem16, CL D3 /1ROR reg/mem16, imm8C1 /1 ibRotate a 16-bit register or memory location right the number ofbits specified in the CL register.Rotate a 16-bit register or memory location right the number ofbits specified by an 8-bit immediate value.ROR reg/mem32, 1 D1 /1 Rotate a 32-bit register or memory location right 1 bit.ROR reg/mem32, CL D3 /1ROR reg/mem32, imm8C1 /1 ibRotate a 32-bit register or memory location right the number ofbits specified in the CL register.Rotate a 32-bit register or memory location right the number ofbits specified by an 8-bit immediate value.ROR reg/mem64, 1 D1 /1 Rotate a 64-bit register or memory location right 1 bit.ROR 253
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