Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionGeneral protection,#GPGeneral protection,#GP(selector)RealVirtual8086 Protected Cause of ExceptionX X X The target offset exceeded the code segment limit or was non-canonical.XXThe return code selector was a null selector.The return stack selector was a null selector and the return mode wasnon-64-bit mode or CPL was 3.XXXXXXXXThe return code or stack descriptor exceeded the descriptor tablelimit.The return code or stack selector’s TI bit was set but the LDT selectorwas a null selector.The segment descriptor for the return code was not a code segment.The RPL of the return code segment selector was less than the CPL.The return code segment was non-conforming and the segmentselector’s DPL was not equal to the RPL of the code segment’s segmentselector.The return code segment was conforming and the segment selector’sDPL was greater than the RPL of the code segment’s segment selectorThe segment descriptor for the return stack was not a writable datasegment.The stack segment descriptor DPL was not equal to the RPL of thereturn code segment selector.X The stack segment selector RPL was not equal to the RPL of the returncode segment selector.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned-memory reference was performed while alignmentchecking was enabled.250 RET (Far)
24594 Rev. 3.10 February 2005 AMD64 TechnologyROLRotate LeftRotates the bits of a register or memory location (first operand) to the left (toward themore significant bit positions) by the number of bit positions in an unsignedimmediate value or the CL register (second operand). The bits rotated out left arerotated back in at the right end (lsb) of the first operand location.The processor masks the upper three bits of the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, it masksthe upper two bits of the count, providing a count in the range of 0 to 63.After completing the rotation, the instruction sets the CF flag to the last bit rotatedout (the lsb of the result). For 1-bit rotates, the instruction sets the OF flag to theexclusive OR of the CF bit (after the rotate) and the most significant bit of the result.When the rotate count is greater than 1, the OF flag is undefined. When the rotatecount is 0, no flags are affected.Mnemonic Opcode DescriptionROL reg/mem8, 1 D0 /0 Rotate an 8-bit register or memory operand left 1 bit.ROL reg/mem8, CL D2 /0ROL reg/mem8, imm8C0 /0 ibRotate an 8-bit register or memory operand left the number ofbits specified in the CL register.Rotate an 8-bit register or memory operand left the number ofbits specified by an 8-bit immediate value.ROL reg/mem16, 1 D1 /0 Rotate a 16-bit register or memory operand left 1 bit.ROL reg/mem16, CL D3 /0ROL reg/mem16, imm8C1 /0 ibRotate a 16-bit register or memory operand left the number ofbits specified in the CL register.Rotate a 16-bit register or memory operand left the number ofbits specified by an 8-bit immediate value.ROL reg/mem32, 1 D1 /0 Rotate a 32-bit register or memory operand left 1 bit.ROL reg/mem32, CL D3 /0ROL reg/mem32, imm8C1 /0 ibRotate a 32-bit register or memory operand left the number ofbits specified in the CL register.Rotate a 32-bit register or memory operand left the number ofbits specified by an 8-bit immediate value.ROL reg/mem64, 1 D1 /0 Rotate a 64-bit register or memory operand left 1 bit.ROL 251
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24594 Rev. 3.10 February 2005 AMD64 TechnologyROLRotate LeftRotates the bits of a register or memory location (first oper<strong>and</strong>) to the left (toward themore significant bit positions) by the number of bit positions in an unsignedimmediate value or the CL register (second oper<strong>and</strong>). The bits rotated out left arerotated back in at the right end (lsb) of the first oper<strong>and</strong> location.The processor masks the upper three bits of the count oper<strong>and</strong>, thus restricting thecount to a number between 0 <strong>and</strong> 31. When the destination is 64 bits wide, it masksthe upper two bits of the count, providing a count in the range of 0 to 63.After completing the rotation, the instruction sets the CF flag to the last bit rotatedout (the lsb of the result). For 1-bit rotates, the instruction sets the OF flag to theexclusive OR of the CF bit (after the rotate) <strong>and</strong> the most significant bit of the result.When the rotate count is greater than 1, the OF flag is undefined. When the rotatecount is 0, no flags are affected.Mnemonic Opcode DescriptionROL reg/mem8, 1 D0 /0 Rotate an 8-bit register or memory oper<strong>and</strong> left 1 bit.ROL reg/mem8, CL D2 /0ROL reg/mem8, imm8C0 /0 ibRotate an 8-bit register or memory oper<strong>and</strong> left the number ofbits specified in the CL register.Rotate an 8-bit register or memory oper<strong>and</strong> left the number ofbits specified by an 8-bit immediate value.ROL reg/mem16, 1 D1 /0 Rotate a 16-bit register or memory oper<strong>and</strong> left 1 bit.ROL reg/mem16, CL D3 /0ROL reg/mem16, imm8C1 /0 ibRotate a 16-bit register or memory oper<strong>and</strong> left the number ofbits specified in the CL register.Rotate a 16-bit register or memory oper<strong>and</strong> left the number ofbits specified by an 8-bit immediate value.ROL reg/mem32, 1 D1 /0 Rotate a 32-bit register or memory oper<strong>and</strong> left 1 bit.ROL reg/mem32, CL D3 /0ROL reg/mem32, imm8C1 /0 ibRotate a 32-bit register or memory oper<strong>and</strong> left the number ofbits specified in the CL register.Rotate a 32-bit register or memory oper<strong>and</strong> left the number ofbits specified by an 8-bit immediate value.ROL reg/mem64, 1 D1 /0 Rotate a 64-bit register or memory oper<strong>and</strong> left 1 bit.ROL 251
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