Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005RCRRotate Through Carry RightRotates the bits of a register or memory location (first operand) to the right (towardthe less significant bit positions) and through the carry flag by the number of bitpositions in an unsigned immediate value or the CL register (second operand). Thebits rotated through the carry flag are rotated back in at the left end (msb) of the firstoperand location.The processor masks the upper three bits in the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, theprocessor masks the upper two bits of the count, providing a count in the range of 0 to63.For 1-bit rotates, the instruction sets the OF flag to the exclusive OR of the CF flag(before the rotate) and the most significant bit of the original value. When the rotatecount is greater than 1, the OF flag is undefined. When the rotate count is 0, no flagsare affected.Mnemonic Opcode DescriptionRCR reg/mem8, 1 D0 /3RCR reg/mem8,CL D2 /3RCR reg/mem8,imm8C0 /3 ibRCR reg/mem16,1 D1 /3RCR reg/mem16,CL D3 /3RCR reg/mem16, imm8C1 /3 ibRCR reg/mem32,1 D1 /3Rotate the 9 bits consisting of the carry flag and an 8-bit registeror memory location right 1 bit.Rotate the 9 bits consisting of the carry flag and an 8-bit registeror memory location right the number of bits specified in the CLregister.Rotate the 9 bits consisting of the carry flag and an 8-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.Rotate the 17 bits consisting of the carry flag and a 16-bit registeror memory location right 1 bit.Rotate the17 bits consisting of the carry flag and a 16-bit registeror memory location right the number of bits specified in the CLregister.Rotate the 17 bits consisting of the carry flag and a 16-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.Rotate the 33 bits consisting of the carry flag and a 32-bit registeror memory location right 1 bit.242 RCR
24594 Rev. 3.10 February 2005 AMD64 TechnologyMnemonic Opcode DescriptionRCR reg/mem32,CL D3 /3Rotate 33 bits consisting of the carry flag and a 32-bit register ormemory location right the number of bits specified in the CLregister.RCR reg/mem32, imm8C1 /3 ibRotate the 33 bits consisting of the carry flag and a 32-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.RCR reg/mem64,1 D1 /3RCR reg/mem64,CL D3 /3Rotate the 65 bits consisting of the carry flag and a 64-bit registeror memory location right 1 bit.Rotate 65 bits consisting of the carry flag and a 64-bit register ormemory location right the number of bits specified in the CLregister.RCR reg/mem64, imm8Related InstructionsRCL, ROR, ROLrFLAGS AffectedC1 /3 ibRotate the 65 bits consisting of the carry flag and a 64-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFMM21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XXThe destination operand was in a non-writable segment.A null data segment was used to reference memory.RCR 243
- Page 222 and 223: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 224 and 225: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 226 and 227: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 228 and 229: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 230 and 231: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 232 and 233: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 234 and 235: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 236 and 237: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 238 and 239: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 240 and 241: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 242 and 243: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 244 and 245: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 246 and 247: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 248 and 249: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 250 and 251: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 252 and 253: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 254 and 255: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 256 and 257: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 258 and 259: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 260 and 261: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 262 and 263: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 264 and 265: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 266 and 267: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 268 and 269: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 270 and 271: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 274 and 275: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 276 and 277: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 278 and 279: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 280 and 281: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 282 and 283: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 284 and 285: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 286 and 287: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 288 and 289: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 290 and 291: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 292 and 293: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 294 and 295: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 296 and 297: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 298 and 299: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 300 and 301: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 302 and 303: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 304 and 305: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 306 and 307: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 308 and 309: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 310 and 311: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 312 and 313: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 314 and 315: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 316 and 317: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 318 and 319: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 320 and 321: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 TechnologyMnemonic Opcode DescriptionRCR reg/mem32,CL D3 /3Rotate 33 bits consisting of the carry flag <strong>and</strong> a 32-bit register ormemory location right the number of bits specified in the CLregister.RCR reg/mem32, imm8C1 /3 ibRotate the 33 bits consisting of the carry flag <strong>and</strong> a 32-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.RCR reg/mem64,1 D1 /3RCR reg/mem64,CL D3 /3Rotate the 65 bits consisting of the carry flag <strong>and</strong> a 64-bit registeror memory location right 1 bit.Rotate 65 bits consisting of the carry flag <strong>and</strong> a 64-bit register ormemory location right the number of bits specified in the CLregister.RCR reg/mem64, imm8Related <strong>Instructions</strong>RCL, ROR, ROLrFLAGS AffectedC1 /3 ibRotate the 65 bits consisting of the carry flag <strong>and</strong> a 64-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFMM21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, <strong>and</strong> 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XXThe destination oper<strong>and</strong> was in a non-writable segment.A null data segment was used to reference memory.RCR 243