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AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionRCL reg/mem32, CL D3 /2Rotate 33 bits consisting of the carry flag and a 32-bit register ormemory location left the number of bits specified in the CLregister.RCL reg/mem32, imm8C1 /2 ibRotate the 33 bits consisting of the carry flag and a 32-bit registeror memory location left the number of bits specified by an 8-bitimmediate value.RCL reg/mem64, 1 D1 /2RCL reg/mem64, CL D3 /2Rotate the 65 bits consisting of the carry flag and a 64-bit registeror memory location left 1 bit.Rotate the 65 bits consisting of the carry flag and a 64-bit registeror memory location left the number of bits specified in the CLregister.RCL reg/mem64, imm8Related InstructionsRCR, ROL, RORrFLAGS AffectedC1 /2 ibRotates the 65 bits consisting of the carry flag and a 64-bitregister or memory location left the number of bits specified byan 8-bit immediate value.ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFMM21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XXThe destination operand was in a non-writable segment.A null data segment was used to reference memory.240 RCL
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionRealVirtual8086 Protected Cause of ExceptionPage fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.RCL 241
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