Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005PREFETCHlevelPrefetch Data to Cache Level levelLoads a cache line from the specified memory address into the data-cache levelspecified by the locality reference bits 5–3 of the ModRM byte. Table 3-16 on page 233lists the locality reference options for the instruction.This instruction loads a cache line even if the mem8 address is not aligned with thestart of the line. If the cache line is already contained in a cache level that is lowerthan the specified locality reference, or if a memory fault is detected, a bus cycle isnot initiated and the instruction is treated as a NOP.The operation of this instruction is implementation-dependent. The processorimplementation can ignore or change this instruction. The size of the cache line alsodepends on the implementation, with a minimum size of 32 bytes. AMD processorsalias PREFETCH1 and PREFETCH2 to PREFETCH0. For details on the use of thisinstruction, see the software-optimization documentation relating to particularhardware implementations.Mnemonic Opcode DescriptionPREFETCHNTA mem8 0F 18 /0 Move data closer to the processor using the NTA reference.PREFETCHT0 mem8 0F 18 /1 Move data closer to the processor using the T0 reference.PREFETCHT1 mem8 0F 18 /2 Move data closer to the processor using the T1 reference.PREFETCHT2 mem8 0F 18 /3 Move data closer to the processor using the T2 reference.232 PREFETCHlevel
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable 3-16.Locality References for the Prefetch InstructionsLocalityReferenceNTAT0T1T2DescriptionNon-Temporal Access—Move the specified data into the processor with minimumcache pollution. This is intended for data that will be used only once, rather thanrepeatedly. The specific technique for minimizing cache pollution isimplementation-dependent and may include such techniques as allocating spacein a software-invisible buffer, allocating a cache line in only a single way, etc. Fordetails, see the software-optimization documentation for a particular hardwareimplementation.All Cache Levels—Move the specified data into all cache levels.Level 2 and Higher—Move the specified data into all cache levels except 0th level(L1) cache.Level 3 and Higher—Move the specified data into all cache levels except 0th level(L1) and 1st level (L2) caches.Related InstructionsPREFETCH, PREFETCHWrFLAGS AffectedNoneExceptionsNonePREFETCHlevel 233
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24594 Rev. 3.10 February 2005 AMD64 TechnologyTable 3-16.Locality References for the Prefetch <strong>Instructions</strong>LocalityReferenceNTAT0T1T2DescriptionNon-Temporal Access—Move the specified data into the processor with minimumcache pollution. This is intended for data that will be used only once, rather thanrepeatedly. The specific technique for minimizing cache pollution isimplementation-dependent <strong>and</strong> may include such techniques as allocating spacein a software-invisible buffer, allocating a cache line in only a single way, etc. Fordetails, see the software-optimization documentation for a particular hardwareimplementation.All Cache Levels—Move the specified data into all cache levels.Level 2 <strong>and</strong> Higher—Move the specified data into all cache levels except 0th level(L1) cache.Level 3 <strong>and</strong> Higher—Move the specified data into all cache levels except 0th level(L1) <strong>and</strong> 1st level (L2) caches.Related <strong>Instructions</strong>PREFETCH, PREFETCHWrFLAGS AffectedNoneExceptionsNonePREFETCHlevel 233
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