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AMD64 Technology 24594 Rev. 3.10 February 2005PREFETCHxPREFETCHWPrefetch L1 Data-Cache LinePREFETCH and PREFETCHW are 3DNow! instructions. They load a cache line intothe L1 data cache from the specified memory address. The PREFETCH instructionloads a cache line even if the mem8 address is not aligned with the start of the line. Ifa cache hit occurs, or if a memory fault is detected, no bus cycle is initiated, and theinstruction is treated as a NOP.The PREFETCHW instruction loads the prefetched line and sets the cache-line stateto Modified, in anticipation of subsequent data writes to the line. The PREFETCHinstruction, by contrast, typically (depending on hardware implementation) sets thecache-line state to Exclusive.The opcodes for the instructions include the ModRM byte, and only the memory formof ModRM is valid. The register form of ModRM causes an invalid-opcode exception.Because there is no destination register, the three destination register field bits of theModRM byte define the type of prefetch to be performed. The bit patterns 000b and001b define the PREFETCH and PREFETCHW instructions, respectively. All otherbit patterns are reserved for future use.The reserved PREFETCH types do not result in an invalid-opcode exception ifexecuted. Instead, for forward compatibility with future processors that mayimplement additional forms of the PREFETCH instruction, all reserved PREFETCHtypes are implemented as synonyms of the basic PREFETCH type (the PREFETCHinstruction with type 000b).The operation of these instructions is implementation-dependent. The processorimplementation can ignore or change these instructions. The size of the cache linealso depends on the implementation, with a minimum size of 32 bytes. For details onthe use of this instruction, see the data sheet or other software-optimizationdocumentation relating to particular hardware implementations.These instructions are 3DNow! instructions; check the status of EDX bit 31 of CPUIDextended function 8000_0001h; check EDX bit 25 of CPUID extended function8000_0001h to verify that the processor supports long mode.230 PREFETCHx
24594 Rev. 3.10 February 2005 AMD64 TechnologyMnemonic Opcode DescriptionPREFETCH mem8 0F 0D /0 Prefetch processor cache line into L1 data cache.PREFETCHW mem8 0F 0D /1Prefetch processor cache line into L1 data cache and mark itmodified.Related InstructionsPREFETCHlevelrFLAGS AffectedNoneExceptionsException (vector)Invalid opcode, #UDRealXVirtual8086 Protected Cause of ExceptionXXThe AMD 3DNow! instructions are not supported, as indicatedby EDX bit 31 of CPUID extended function8000_0001h; and Long Mode is not supported, as indicatedby EDX bit 29 of CPUID extended function 8000_0001h.XXXThe operand was a register.PREFETCHx 231
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