Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005POPAxPOPADPOP All GPRsPops words or doublewords from the stack into the general-purpose registers in thefollowing order: eDI, eSI, eBP, eSP (image is popped and discarded), eBX, eDX, eCX,and eAX. The instruction increments the stack pointer by 16 or 32, depending on theoperand size.Using the POPA or POPAD instructions in 64-bit mode generates an invalid-opcodeexception.Mnemonic Opcode DescriptionPOPA 61POPAD 61Pop the DI, SI, BP, SP, BX, DX, CX, and AX registers.(Invalid in 64-bit mode.)Pop the EDI, ESI, EBP, ESP, EBX, EDX, ECX, and EAX registers.(Invalid in 64-bit mode.)Related InstructionsPUSHA, PUSHADrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode (#UD) X This instruction was executed in 64-bit mode.Stack, #SS X X X A memory address exceeded the stack segment limit.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.226 POPAx
24594 Rev. 3.10 February 2005 AMD64 TechnologyPOPFxPOPFDPOPFQPOP to rFLAGSPops a word, doubleword, or quadword from the stack into the rfLAGS register andthen increments the stack pointer by 2, 4, or 8, depending on the operand size.In protected or real mode, all the non-reserved flags in the rFLAGS register can bemodified, except the VIP, VIF, and VM flags, which are unchanged. In protected mode,at a privilege level greater than 0 the IOPL is also unchanged. The instruction altersthe interrupt flag (IF) only when the CPL is less than or equal to the IOPL.In virtual-8086 mode, if IOPL field is less than 3, attempting to execute a POPFx orPUSHFx instruction while VME is not enabled, or the operand size is not 16-bit,generates a #GP exception.In 64-bit mode, this instruction defaults to a 64-bit operand size; there is no prefixavailable to encode a 32-bit operand size.Mnemonic Opcode DescriptionPOPF 9D Pop a word from the stack into the FLAGS register.POPFDAction// See “Pseudocode Definitions” on page 49.POPF_START:IF (REAL_MODE)POPF_REALELSIF (PROTECTED_MODE)POPF_PROTECTEDELSE // (VIRTUAL_MODE)POPF_VIRTUAL9DPop a double word from the stack into the EFLAGS register. (Noprefix for encoding this in 64-bit mode.)POPFQ 9D Pop a quadword from the stack to the RFLAGS register.POPF_REAL:POP.v temp_RFLAGSPOPFx 227
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24594 Rev. 3.10 February 2005 AMD64 TechnologyPOPFxPOPFDPOPFQPOP to rFLAGSPops a word, doubleword, or quadword from the stack into the rfLAGS register <strong>and</strong>then increments the stack pointer by 2, 4, or 8, depending on the oper<strong>and</strong> size.In protected or real mode, all the non-reserved flags in the rFLAGS register can bemodified, except the VIP, VIF, <strong>and</strong> VM flags, which are unchanged. In protected mode,at a privilege level greater than 0 the IOPL is also unchanged. The instruction altersthe interrupt flag (IF) only when the CPL is less than or equal to the IOPL.In virtual-8086 mode, if IOPL field is less than 3, attempting to execute a POPFx orPUSHFx instruction while VME is not enabled, or the oper<strong>and</strong> size is not 16-bit,generates a #GP exception.In 64-bit mode, this instruction defaults to a 64-bit oper<strong>and</strong> size; there is no prefixavailable to encode a 32-bit oper<strong>and</strong> size.Mnemonic Opcode DescriptionPOPF 9D Pop a word from the stack into the FLAGS register.POPFDAction// See “Pseudocode Definitions” on page 49.POPF_START:IF (REAL_MODE)POPF_REALELSIF (PROTECTED_MODE)POPF_PROTECTEDELSE // (VIRTUAL_MODE)POPF_VIRTUAL9DPop a double word from the stack into the EFLAGS register. (Noprefix for encoding this in 64-bit mode.)POPFQ 9D Pop a quadword from the stack to the RFLAGS register.POPF_REAL:POP.v temp_RFLAGSPOPFx 227
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