Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005MULUnsigned MultiplyMultiplies the unsigned byte, word, doubleword, or quadword value in the specifiedregister or memory location by the value in AL, AX, EAX, or RAX and stores the resultin AX, DX:AX, EDX:EAX, or RDX:RAX (depending on the operand size). It puts thehigh-order bits of the product in AH, DX, EDX, or RDX.If the upper half of the product is non-zero, the instruction sets the carry flag (CF) andoverflow flag (OF) both to 1. Otherwise, it clears CF and OF to 0. The other arithmeticflags (SF, ZF, AF, PF) are undefined.Mnemonic Opcode DescriptionMUL reg/mem8 F6 /4MUL reg/mem16 F7 /4MUL reg/mem32 F7 /4MUL reg/mem64 F7 /4Multiplies an 8-bit register or memory operand by the contentsof the AL register and stores the result in the AX register.Multiplies a 16-bit register or memory operand by the contents ofthe AX register and stores the result in the DX:AX register.Multiplies a 32-bit register or memory operand by the contents ofthe EAX register and stores the result in the EDX:EAX register.Multiplies a 64-bit register or memory operand by the contentsof the RAX register and stores the result in the RDX:RAX register.Related InstructionsDIV210 MUL
24594 Rev. 3.10 February 2005 AMD64 TechnologyrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM U U U U M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference is performed while alignmentchecking was enabled.MUL 211
- Page 190 and 191: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 192 and 193: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 194 and 195: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 196 and 197: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 198 and 199: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 200 and 201: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 202 and 203: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 204 and 205: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 206 and 207: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 208 and 209: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 210 and 211: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 212 and 213: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 214 and 215: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 216 and 217: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 218 and 219: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 220 and 221: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 222 and 223: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 224 and 225: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 226 and 227: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 228 and 229: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 230 and 231: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 232 and 233: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 234 and 235: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 236 and 237: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 238 and 239: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 242 and 243: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 244 and 245: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 246 and 247: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 248 and 249: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 250 and 251: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 252 and 253: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 254 and 255: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 256 and 257: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 258 and 259: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 260 and 261: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 262 and 263: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 264 and 265: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 266 and 267: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 268 and 269: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 270 and 271: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 272 and 273: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 274 and 275: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 276 and 277: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 278 and 279: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 280 and 281: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 282 and 283: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 284 and 285: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 286 and 287: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 288 and 289: AMD64 Technology 24594 Rev. 3.10 Fe
AMD64 Technology 24594 Rev. 3.10 February 2005MULUnsigned MultiplyMultiplies the unsigned byte, word, doubleword, or quadword value in the specifiedregister or memory location by the value in AL, AX, EAX, or RAX <strong>and</strong> stores the resultin AX, DX:AX, EDX:EAX, or RDX:RAX (depending on the oper<strong>and</strong> size). It puts thehigh-order bits of the product in AH, DX, EDX, or RDX.If the upper half of the product is non-zero, the instruction sets the carry flag (CF) <strong>and</strong>overflow flag (OF) both to 1. Otherwise, it clears CF <strong>and</strong> OF to 0. The other arithmeticflags (SF, ZF, AF, PF) are undefined.Mnemonic Opcode DescriptionMUL reg/mem8 F6 /4MUL reg/mem16 F7 /4MUL reg/mem32 F7 /4MUL reg/mem64 F7 /4Multiplies an 8-bit register or memory oper<strong>and</strong> by the contentsof the AL register <strong>and</strong> stores the result in the AX register.Multiplies a 16-bit register or memory oper<strong>and</strong> by the contents ofthe AX register <strong>and</strong> stores the result in the DX:AX register.Multiplies a 32-bit register or memory oper<strong>and</strong> by the contents ofthe EAX register <strong>and</strong> stores the result in the EDX:EAX register.Multiplies a 64-bit register or memory oper<strong>and</strong> by the contentsof the RAX register <strong>and</strong> stores the result in the RDX:RAX register.Related <strong>Instructions</strong>DIV210 MUL
Change language