Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005MOVSXDMove with Sign-Extend DoublewordCopies the 32-bit value in a register or memory location (second operand) into a 64-bitregister (first operand), extending the most significant bit of the 32-bit value into allhigher bits of the 64-bit register.This instruction requires the REX prefix 64-bit operand size bit (REX.W) to be set to 1to sign-extend a 32-bit source operand to a 64-bit result. Without the REX operandsizeprefix, the operand size will be 32 bits, the default for 64-bit mode, and the sourceis zero-extended into a 64-bit register. With a 16-bit operand size, only 16 bits arecopied, without modifying the upper 48 bits in the destination.This instruction is available only in 64-bit mode. In legacy or compatibility mode thisopcode is interpreted as ARPL.Mnemonic Opcode DescriptionMOVSXD reg64, reg/mem32 63 /rMove the contents of a 32-bit register or memory operand to a64-bit register with sign extension.Related InstructionsMOVSX, MOVZXrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X A memory address was non-canonical.General protection,X A memory address was non-canonical.#GPPage fault, #PF X A page fault resulted from the execution of the instruction.Alignment check, #AC X An unaligned memory reference was performed while alignmentchecking was enabled.208 MOVSXD
24594 Rev. 3.10 February 2005 AMD64 TechnologyMOVZXMove with Zero-ExtensionCopies the value in a register or memory location (second operand) into a register(first operand), zero-extending the value to fit in the destination register. Theoperand-size attribute determines the size of the zero-extended value.Mnemonic Opcode DescriptionMOVZX reg16, reg/mem8 0F B6 /rMOVZX reg32, reg/mem8 0F B6 /rMOVZX reg64, reg/mem8 0F B6 /rMOVZX reg32, reg/mem16 0F B7 /rMOVZX reg64, reg/mem16 0F B7 /rMove the contents of an 8-bit register or memory operand to a16-bit register with zero-extension.Move the contents of an 8-bit register or memory operand to a32-bit register with zero-extension.Move the contents of an 8-bit register or memory operand to a64-bit register with zero-extension.Move the contents of a 16-bit register or memory operand to a32-bit register with zero-extension.Move the contents of a 16-bit register or memory operand to a64-bit register with zero-extension.Related InstructionsMOVSXD, MOVSXrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.MOVZX 209
- Page 188 and 189: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 190 and 191: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 192 and 193: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 194 and 195: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 196 and 197: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 198 and 199: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 200 and 201: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 202 and 203: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 204 and 205: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 206 and 207: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 208 and 209: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 210 and 211: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 212 and 213: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 214 and 215: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 216 and 217: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 218 and 219: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 220 and 221: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 222 and 223: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 224 and 225: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 226 and 227: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 228 and 229: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 230 and 231: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 232 and 233: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 234 and 235: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 236 and 237: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 240 and 241: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 242 and 243: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 244 and 245: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 246 and 247: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 248 and 249: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 250 and 251: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 252 and 253: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 254 and 255: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 256 and 257: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 258 and 259: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 260 and 261: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 262 and 263: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 264 and 265: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 266 and 267: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 268 and 269: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 270 and 271: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 272 and 273: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 274 and 275: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 276 and 277: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 278 and 279: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 280 and 281: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 282 and 283: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 284 and 285: AMD64 Technology 24594 Rev. 3.10 Fe
- Page 286 and 287: AMD64 Technology 24594 Rev. 3.10 Fe
24594 Rev. 3.10 February 2005 AMD64 TechnologyMOVZXMove with Zero-ExtensionCopies the value in a register or memory location (second oper<strong>and</strong>) into a register(first oper<strong>and</strong>), zero-extending the value to fit in the destination register. Theoper<strong>and</strong>-size attribute determines the size of the zero-extended value.Mnemonic Opcode DescriptionMOVZX reg16, reg/mem8 0F B6 /rMOVZX reg32, reg/mem8 0F B6 /rMOVZX reg64, reg/mem8 0F B6 /rMOVZX reg32, reg/mem16 0F B7 /rMOVZX reg64, reg/mem16 0F B7 /rMove the contents of an 8-bit register or memory oper<strong>and</strong> to a16-bit register with zero-extension.Move the contents of an 8-bit register or memory oper<strong>and</strong> to a32-bit register with zero-extension.Move the contents of an 8-bit register or memory oper<strong>and</strong> to a64-bit register with zero-extension.Move the contents of a 16-bit register or memory oper<strong>and</strong> to a32-bit register with zero-extension.Move the contents of a 16-bit register or memory oper<strong>and</strong> to a64-bit register with zero-extension.Related <strong>Instructions</strong>MOVSXD, MOVSXrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.<strong>General</strong> protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.MOVZX 209
Change language