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AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionsExceptionInvalid opcode, #UDRealXVirtual8086 Protected Cause of ExceptionXXThe SSE2 instructions are not supported, as indicated by EDXbit 26 of CPUID extended function 1.XXXThe operating-system FXSAVE/FXRSTOR support bit (OSFXSR)of CR4 was cleared to 0.Device not available,#NMX X X The emulate bit (EM) of CR0 was set to 1.X X X The task-switch bit (TS) of CR0 was set to 1.202 MOVMSKPS
24594 Rev. 3.10 February 2005 AMD64 TechnologyMOVNTIMove Non-Temporal Doubleword or QuadwordStores a value in a 32-bit or 64-bit general-purpose register (second operand) in amemory location (first operand). This instruction indicates to the processor that thedata is non-temporal and is unlikely to be used again soon. The processor treats thestore as a write-combining (WC) memory write, which minimizes cache pollution. Theexact method by which cache pollution is minimized depends on the hardwareimplementation of the instruction. For further information, see “MemoryOptimization” in Volume 1.The MOVNTI instruction is weakly-ordered with respect to other instructions thatoperate on memory. Software should use an SFENCE instruction to force strongmemory ordering of MOVNTI with respect to other stores.Support for the MOVNTI instruction is indicated when the SSE2 bit (bit 26) is set to 1in EDX after executing CPUID standard function 1.Mnemonic Opcode DescriptionMOVNTI mem32, reg32 0F C3 /rMOVNTI mem64, reg64 0F C3 /rStores a 32-bit general-purpose register value into a 32-bitmemory location, minimizing cache pollution.Stores a 64-bit general-purpose register value into a 64-bitmemory location, minimizing cache pollution.Related InstructionsMOVNTDQ, MOVNTPD, MOVNTPS, MOVNTQrFLAGS AffectedNoneExceptionsException (vector) RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The SSE2 instructions are not supported, as indicated by EDXbit 26 of CPUID standard function 1.Stack, #SS X X X A memory address exceeded the stack segment limit or wasnon-canonical.MOVNTI 203
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