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AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionsException (vector)Invalid opcode, #UDRealXVirtual8086 Protected Cause of ExceptionXXThe SSE2 instructions are not supported, as indicated by EDXbit 26 of CPUID standard function 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Device not available,#NMX X X The emulate bit (EM) of CR0 was set to 1.X X X The task-switch bit (TS) of CR0 was set to 1.200 MOVMSKPD
24594 Rev. 3.10 February 2005 AMD64 TechnologyMOVMSKPSExtract Packed Single-Precision Floating-PointSign MaskMoves the sign bits of four packed single-precision floating-point values in an XMMregister (second operand) to the four low-order bits of a general-purpose register (firstoperand) with zero-extension.The MOVMSKPD instruction is an SSE2 instruction; Check the status of EDX bit 26 ofCPUID standard function 1 to verify that the processor supports this function.Mnemonic Opcode DescriptionMOVMSKPS reg32, xmm 0F 50 /rMove sign bits 127, 95, 63, 31 in an XMM register to a 32-bitgeneral-purpose register.reg32xmm3103 0 127 95 63 310copy signcopy signcopy signcopy signmovmskps.epsRelated InstructionsMOVMSKPD, PMOVMSKBrFLAGS AffectedNoneMXCSR Flags AffectedNoneMOVMSKPS 201
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