Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologyMOVMSKPDExtract Packed Double-Precision Floating-PointSign MaskMoves the sign bits of two packed double-precision floating-point values in an XMMregister (second operand) to the two low-order bits of a general-purpose register (firstoperand) with zero-extension.The MOVMSKPD instruction is an SSE2 instruction; Check the status of EDX bit 26 ofCPUID standard function 1 to verify that the processor supports this function.Mnemonic Opcode DescriptionMOVMSKPD reg32, xmm 66 0F 50 /rMove sign bits 127 and 63 in an XMM register to a 32-bit generalpurposeregister.reg32xmm3110127 63 00copy signcopy signmovmskpd.epsRelated InstructionsMOVMSKPS, PMOVMSKBrFLAGS AffectedNoneMXCSR Flags AffectedNoneMOVMSKPD 199