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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005MOVMoveCopies an immediate value or the value in a general-purpose register, segmentregister, or memory location (second oper<strong>and</strong>) to a general-purpose register, segmentregister, or memory location. The source <strong>and</strong> destination must be the same size (byte,word, doubleword, or quadword) <strong>and</strong> cannot both be memory locations.In opcodes A0 through A3, the memory offsets (called moffsets) are address sized. In64-bit mode, memory offsets default to 64 bits. Opcodes A0–A3, in 64-bit mode, are theonly cases that support a 64-bit offset value. (In all other cases, offsets <strong>and</strong>displacements are a maximum of 32 bits.) The B8 through BF (B8 +rq) opcodes, in 64-bit mode, are the only cases that support a 64-bit immediate value (in all other cases,immediate values are a maximum of 32 bits).When reading segment-registers with a 32-bit oper<strong>and</strong> size, the processor zero-extendsthe 16-bit selector results to 32 bits. When reading segment-registers with a 64-bitoper<strong>and</strong> size, the processor zero-extends the 16-bit selector to 64 bits. If thedestination oper<strong>and</strong> specifies a segment register (DS, ES, FS, GS, or SS), the sourceoper<strong>and</strong> must be a valid segment selector.It is possible to move a null segment selector value (0000–0003h) into the DS, ES, FS,or GS register. This action does not cause a general protection fault, but a subsequentreference to such a segment does cause a #GP exception. For more information aboutsegment selectors, see “Segment Selectors <strong>and</strong> Registers” on page 82.When the MOV instruction is used to load the SS register, the processor blocksexternal interrupts until after the execution of the following instruction. This actionallows the following instruction to be a MOV instruction to load a stack pointer intothe ESP register (MOV ESP,val) before an interrupt occurs. However, the LSSinstruction provides a more efficient method of loading SS <strong>and</strong> ESP.Attempting to use the MOV instruction to load the CS register generates an invalidopcode exception (#UD). Use the far JMP, CALL, or RET instructions to load the CSregister.To initialize a register to 0, rather than using a MOV instruction, it may be moreefficient to use the XOR instruction with identical destination <strong>and</strong> source oper<strong>and</strong>s.192 MOV

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