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AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionLOOPNZ rel8off E0 cb Decrement rCX, then Jump short if rCX is not 0 and ZF is 0.LOOPZ rel8off E1 cb Decrement rCX, then Jump short if rCX is not 0 and ZF is 1.Related InstructionsNonerFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X X The target offset exceeded the code segment limit or was non-canonical.190 LOOPcc
24594 Rev. 3.10 February 2005 AMD64 TechnologyMFENCEMemory FenceActs as a barrier to force strong memory ordering (serialization) between load andstore instructions preceding the MFENCE, and load and store instructions that followthe MFENCE. A weakly-ordered memory system allows the hardware to reorder readsand writes between the processor and memory. The MFENCE instruction guaranteesthat the system completes all previous memory accesses before executing subsequentaccesses.The MFENCE instruction is weakly-ordered with respect to data and instructionprefetches. Speculative loads initiated by the processor, or specified explicitly usingcache-prefetch instructions, can be reordered around an MFENCE.In addition to load and store instructions, the MFENCE instruction is strongly orderedwith respect to other MFENCE instructions, LFENCE instructions, SFENCEinstructions, serializing instructions, and CLFLUSH instructions.Support for the MFENCE instruction is indicated when the SSE2 bit (bit 26) is set to 1in EDX after executing CPUID with standard function 1.Mnemonic Opcode DescriptionMFENCE 0F AE F0 Force strong ordering of (serialized) load and store operations.Related InstructionsLFENCE, SFENCErFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The MFENCE instruction is not supported as indicated by bit 26 ofCPUID standard function 1.MFENCE 191
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