Volume 3: General-Purpose and System Instructions - Stanford ...
Volume 3: General-Purpose and System Instructions - Stanford ... Volume 3: General-Purpose and System Instructions - Stanford ...
AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionLODS mem64ADLoad quadword at DS:rSI into RAX and then increment ordecrement rSI.LODSB AC Load byte at DS:rSI into AL and then increment or decrement rSI.LODSWLODSDLODSQRelated InstructionsMOVSx, STOSxrFLAGS AffectedNoneExceptionsADADADLoad the word at DS:rSI into AX and then increment ordecrement rSI.Load doubleword at DS:rSI into EAX and then increment ordecrement rSI.Load quadword at DS:rSI into RAX and then increment ordecrement rSI.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.188 LODSx
24594 Rev. 3.10 February 2005 AMD64 TechnologyLOOPccLOOPELOOPNELOOPNZLOOPZLoopDecrements the count register (rCX) by 1, then, if rCX is not 0 and the ZF flag meetsthe condition specified by the mnemonic, it jumps to the target instruction specifiedby the signed 8-bit relative offset. Otherwise, it continues with the next instructionafter the LOOPcc instruction.The size of the count register used (CX, ECX, or RCX) depends on the address-sizeattribute of the LOOPcc instruction.The LOOP instruction ignores the state of the ZF flag.The LOOPE and LOOPZ instructions jump if rCX is not 0 and the ZF flag is set to 1. Inother words, the instruction exits the loop (falls through to the next instruction) if rCXbecomes 0 or ZF = 0.The LOOPNE and LOOPNZ instructions jump if rCX is not 0 and ZF flag is cleared to0. In other words, the instruction exits the loop if rCX becomes 0 or ZF = 1.The LOOPcc instruction does not change the state of the ZF flag. Typically, the loopcontains a compare instruction to set or clear the ZF flag.If the jump is taken, the signed displacement is added to the rIP (of the followinginstruction) and the result is truncated to 16, 32, or 64 bits, depending on operandsize.In 64-bit mode, the operand size defaults to 64 bits without the need for a REX prefix,and the processor sign-extends the 8-bit offset before adding it to the RIP.Mnemonic Opcode DescriptionLOOP rel8off E2 cb Decrement rCX, then jump short if rCX is not 0.LOOPE rel8off E1 cb Decrement rCX, then jump short if rCX is not 0 and ZF is 1.LOOPNE rel8off E0 cb Decrement rCX, then Jump short if rCX is not 0 and ZF is 0.LOOPcc 189
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24594 Rev. 3.10 February 2005 AMD64 TechnologyLOOPccLOOPELOOPNELOOPNZLOOPZLoopDecrements the count register (rCX) by 1, then, if rCX is not 0 <strong>and</strong> the ZF flag meetsthe condition specified by the mnemonic, it jumps to the target instruction specifiedby the signed 8-bit relative offset. Otherwise, it continues with the next instructionafter the LOOPcc instruction.The size of the count register used (CX, ECX, or RCX) depends on the address-sizeattribute of the LOOPcc instruction.The LOOP instruction ignores the state of the ZF flag.The LOOPE <strong>and</strong> LOOPZ instructions jump if rCX is not 0 <strong>and</strong> the ZF flag is set to 1. Inother words, the instruction exits the loop (falls through to the next instruction) if rCXbecomes 0 or ZF = 0.The LOOPNE <strong>and</strong> LOOPNZ instructions jump if rCX is not 0 <strong>and</strong> ZF flag is cleared to0. In other words, the instruction exits the loop if rCX becomes 0 or ZF = 1.The LOOPcc instruction does not change the state of the ZF flag. Typically, the loopcontains a compare instruction to set or clear the ZF flag.If the jump is taken, the signed displacement is added to the rIP (of the followinginstruction) <strong>and</strong> the result is truncated to 16, 32, or 64 bits, depending on oper<strong>and</strong>size.In 64-bit mode, the oper<strong>and</strong> size defaults to 64 bits without the need for a REX prefix,<strong>and</strong> the processor sign-extends the 8-bit offset before adding it to the RIP.Mnemonic Opcode DescriptionLOOP rel8off E2 cb Decrement rCX, then jump short if rCX is not 0.LOOPE rel8off E1 cb Decrement rCX, then jump short if rCX is not 0 <strong>and</strong> ZF is 1.LOOPNE rel8off E0 cb Decrement rCX, then Jump short if rCX is not 0 <strong>and</strong> ZF is 0.LOOPcc 189
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